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No need to consider 4 last pkt from 4 queue in master branch:

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Always assume Linux schedule 4 priority queue to 4 FPGA queue via 1 on 1 mapping
This commit is contained in:
Xianjun Jiao 2022-03-28 20:41:00 +02:00
parent 0cbb687387
commit 54c67c7a2f
1 changed files with 4 additions and 2 deletions
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6
driver/tx_intf/tx_intf.c
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@ -243,9 +243,11 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_sym
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
if(fpga_type == LARGE_FPGA) // LARGE FPGA: MAX_NUM_DMA_SYMBOL = 8192
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-200); // when only 200 DMA symbol room left in fifo, stop Linux queue
// tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-(210*5)); // threshold is for room to hold the last 4 packets from 4 queue before stop
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-(210*2));
else if(fpga_type == SMALL_FPGA) // SMALL FPGA: MAX_NUM_DMA_SYMBOL = 4096
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-200); // when only 200 DMA symbol room left in fifo, stop Linux queue
// tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-(210*5)); // threshold is for room to hold the last 4 packets from 4 queue before stop
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-(210*2));
switch(mode)
{