14 Commits

Author	SHA1	Message	Date
mmehari	261bb9eef7	A-MPDU rx aggregation support	2022-01-06 14:13:24 +01:00
Xianjun Jiao	d14d06e508	CSI fuzzer feature -- document to be finished	2021-05-13 17:45:39 +02:00
Xianjun Jiao	913a9e947c	add ack disable register in xpu in case ack needs to be disabled in monitor mode	2021-04-05 21:51:47 +02:00
Xianjun Jiao	aed16d0502	add missing soft decoding api in hw_def.h	2021-04-05 21:50:40 +02:00
Xianjun Jiao	bb0a2c5897	in xpu.v slv_reg19 and slv_reg8 are not twistted anymore. slv_reg6 is added to assist the register map in xpu more clear. separate registers for different purpose. separate registers for dynamic and static configurations in driver (sdr.c).	2021-04-05 21:49:59 +02:00
Jiao Xianjun	55c2866f7c	Merge pull request #54 from lnceballosz/master ... NGI0 - Updating licensing aspects according REUSE	2021-02-03 16:14:49 +01:00
Jiao Xianjun	d5f8d0d664	Update hw_def.h	2021-02-03 15:36:30 +01:00
Lina Ceballos	a6085186d9	adding license and copyright headers	2021-01-20 13:30:12 +01:00
mmehari	6e3730c0c1	Linux queue waking/sleeping decision update: LARGE FPGA models were using small MAX_NUM_DMA_SYMBOL but now is based on /proc/device-tree/model information	2020-12-29 21:33:36 +01:00
Xianjun Jiao	5deb8d18f6	sync internal	2020-12-14 13:32:15 +01:00
Xianjun Jiao	838a9007cf	update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing	2020-06-12 10:50:34 +02:00
Xianjun Jiao	febc5adf73	prepare upgrade	2020-04-27 09:37:04 +02:00
Xianjun Jiao	b73660ad79	prepare for release	2020-03-04 19:39:12 +01:00
Xianjun Jiao	2ee6717882	initial commit	2019-12-10 14:03:47 +01:00