20 Commits

Author	SHA1	Message	Date
Xianjun Jiao	030cdb34ca	Add force ht smoothing option: ... > 1. Leave the module always enabled, so the slv_reg1 is free > 2. Use the slv_reg1 to force ht smoothing > 3. By default, the smoothing option of the receiver is still controlled by the received ht packet	2022-01-28 12:15:49 +01:00
mmehari	23e61e6a29	Avoid equalizer module processing HT_STF symbol	2022-01-04 22:45:47 +01:00
mmehari	0c75a8e8f2	bug fix: remaining packet length calculation	2022-01-04 22:44:31 +01:00
mmehari	8730912d6f	feature update: sampling frequency offset (SFO) compensation	2022-01-04 22:26:57 +01:00
mmehari	48aade0190	provide demod_soft_bits and demod_soft_bits_pos signals out	2022-01-04 22:18:23 +01:00
mmehari	84039d7368	Don't catagorize IQ modulation as Q-BPSK or BPSK when I and Q components have the same magnitude	2022-01-04 22:17:12 +01:00
mmehari	d9649eb614	phase register size reduction: 32bit -> 16bit	2022-01-04 22:10:36 +01:00
mmehari	aaa8ef3ce5	HT/non_HT detection requires at most 9 clocks	2022-01-04 22:05:38 +01:00
mmehari	8bc2d7f0a4	channel smoothing update based on HT-SIG field	2022-01-04 22:03:03 +01:00
mmehari	171ef8b27a	A-MPDU decoding support	2022-01-04 22:01:58 +01:00
Xianjun Jiao	d331e66a31	add necessary port as trigger for iq capture feature in openwifi	2020-10-19 09:22:54 +02:00
Xianjun Jiao	8714c30857	output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux	2020-10-08 10:06:03 +02:00
mmehari	b86951097c	802.11n rx performance fix when used different clock rates (i.e. 100MHz vs 200MHz)	2020-08-30 15:23:07 +02:00
Xianjun Jiao	6a0073ee58	remove debug	2020-06-12 10:24:59 +02:00
mmehari	1f8bb83587	soft decoding support for BPSK, QPSK, 16-QAM and 64-QAM	2019-12-10 13:45:43 +01:00
Xianjun Jiao	2643844f2f	necessary bug fixes and improvements for openwifi	2019-12-10 13:31:16 +01:00
weiliu	10ff8da3d7	port dot11 to zynq	2019-12-10 14:09:31 +01:00
Jinghao Shi	b7361b2feb	fix port pinout	2017-04-21 13:41:49 -04:00
Jinghao Shi	1ad9302fc3	readme	2017-04-03 14:31:25 -04:00
Jinghao Shi	9edf1899bd	verilog init	2017-04-03 12:52:03 -04:00