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648382db74
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702 Commits

Author SHA1 Message Date
Emery Hemingway
648382db74 Align after template expansion 
Clang Cannot align template structs. Also, cannot cast void* to addr_t
in constexpr function.

Issue #3564
 2019-12-19 16:59:03 +01:00
Emery Hemingway
2c510bb7f9 Remove unused lamba capture to fix clang warning 
Issue #3564
 2019-12-19 16:59:03 +01:00
Christian Helmuth
11ef8e1ff2 depot: update recipe hashes 2019-11-28 09:06:39 +01:00
Stefan Kalkowski
4800bcf5a0 hw: correct the i.MX6 Sabrelite timer settings 
Fix #3561
 2019-11-25 15:43:59 +01:00
Christian Prochaska
57d080d4f8 hw: use correct type on IRQ kernel object destruction 
Fixes #3560
 2019-11-25 14:15:39 +01:00
Stefan Kalkowski
af29dcf557 hw: introduce virtualization support for ARMv8 
Ref #3553
 2019-11-21 14:29:36 +01:00
Stefan Kalkowski
f82714f341 vm_session: return vcpu id when creating vcpu 
Ref #3553
 2019-11-21 14:29:36 +01:00
Stefan Kalkowski
02d68fdb97 hw: move arm virtualization to generic place 
Ref #3553
 2019-11-21 14:29:36 +01:00
Stefan Kalkowski
065b9fdb46 base-hw: extend syscalls to five arguments 
Ref #3553
 2019-11-21 14:29:36 +01:00
Christian Helmuth
7ed1d7f11d depot: update recipe hashes 2019-11-19 14:54:14 +01:00
Stefan Kalkowski
8a8aa85726 hw: initialize iomux, ccm and gpc for i.MX8 EVK 
Fix #3534
 2019-11-19 14:42:23 +01:00
Stefan Kalkowski
105b2c9b7a hw: fix gicv3 implementation of clear/set regs 
In addition use uniformly enums for interupt count in register declarations.

Fix #3532
 2019-11-19 14:42:23 +01:00
Stefan Kalkowski
f6435d91fc hw: turn Kernel_object into Genode::Constructible 
Fix #3531
 2019-11-19 14:42:23 +01:00
Stefan Kalkowski
3e3fb63863 hw: enable Genode::raw for bootstrap 
Ref #3531
 2019-11-19 14:42:23 +01:00
Stefan Kalkowski
87a6368ba1 hw: implement multi-processor support for rpi3 
Fix #3522
 2019-11-19 14:42:22 +01:00
Stefan Kalkowski
1cbd77c806 hw: implement multi-processor support for i.MX8 
Fix #3520
 2019-11-19 14:42:22 +01:00
Stefan Kalkowski
e3f82b09d7 hw: instantiate pic object per cpu 
Ref #3520
 2019-11-19 14:42:22 +01:00
Christian Helmuth
4a7b0e99a6 depot: update recipe hashes 2019-09-20 14:14:16 +02:00
Christian Helmuth
b2c59576ae depot: update recipe hashes 2019-08-28 14:36:56 +02:00
Christian Helmuth
312f801f8a depot: update recipe hashes 2019-08-21 13:25:26 +02:00
Sebastian Sumpf
e855638266 hw: add system call for irq mode setting 
Core is not allowd to access the kernel's Pic implementation directly.

fixes #3474
 2019-08-21 13:25:25 +02:00
Christian Helmuth
1c77ea2b03 base-hw: remove other board libs from recipes 2019-08-13 12:02:27 +02:00
Christian Prochaska
4c113182b0 depot: add recipe for base-hw-imx8q_evk 
Issue #3426
 2019-08-13 12:02:27 +02:00
Stefan Kalkowski
7ced122ddc hw: support for i.MX8M Quad EVK 
Fix #3426
 2019-08-13 12:02:27 +02:00
Stefan Kalkowski
6b09ac59f0 hw: enable performance counter for ARMv8 
Ref #3426
 2019-08-13 12:02:27 +02:00
Stefan Kalkowski
ee38504d81 hw: implement update_data_region for ARMv8 
Ref #3426
 2019-08-13 12:02:26 +02:00
Sebastian Sumpf
dd505edd19 hw: GICv3 implementation 
* modern GICv3 implementation
* distributor
* redistributor
* MMIO cpu interface

Ref #3426
 2019-08-13 12:02:26 +02:00
Stefan Kalkowski
fa1aa33f83 hw: sanitize arm trustzone/virtualization services 
Those services are not SoC specific and have to reside at a generic place.

Fix #3445
 2019-08-13 12:02:26 +02:00
Stefan Kalkowski
907de9d37f hw: move timer into board.h 
Unify the generic timer implementation for ARMv7 and ARMv8.

Ref #3445
 2019-08-13 12:02:26 +02:00
Stefan Kalkowski
5c7436bf10 hw: remove SMP variable from board.h 
Whether an SoC has the multiprocessing extensions can be read out
from the identification registers, and does not need to be specified
in each board header.

Ref #3445
 2019-08-13 12:02:26 +02:00
Stefan Kalkowski
0b77e8ea62 hw: consistently move cpu into board namespace 
Ref #3445
 2019-08-13 12:02:26 +02:00
Stefan Kalkowski
875858b2cc hw: integrate interrupt controllers into board.h 
Additionally, unify more implementation details in between different
usage patterns of ARM's generic interrupt controller (v2)

Ref #3445
 2019-08-13 12:02:26 +02:00
Martin Stein
b87e21a392 base-hw: EFI sys-table pointer in platform info 
Ref #3430
 2019-08-13 12:02:03 +02:00
Christian Helmuth
17d32b3e15 depot: update recipe hashes 2019-07-09 09:06:54 +02:00
Stefan Kalkowski
186c35bb09 depot: recipe for base-hw-rpi3 
Ref #3407
 2019-07-09 08:55:23 +02:00
Stefan Kalkowski
90d07741aa hw: support for ARM64 Raspberry Pi 3 
Restriction: enables only cpu core 0 and the timer interrupt by now.

Fix #3405
 2019-07-09 08:55:22 +02:00
Stefan Kalkowski
87015df66c hw: change update_pd to invalidate_tlb 
In the past, the core-only privileged syscall `update_pd` was used only
to invalidate the TLB after removal of page-table entries.
By now, the whole TLB at least for one protection domain got invalidated,
but in preparation for optimization and upcomingARM v8 support,
it is necessary to deliver the virtual memory region that needs to get
invalidated. Moreover, the name of the call shall represent explicitely
that it is used to invalidate the TLB.

Ref #3405
 2019-07-09 08:55:22 +02:00
Stefan Kalkowski
d9a0f76e7a hw: extend long-descriptor page table format 
Ref #3405
 2019-07-09 08:55:22 +02:00
Christian Helmuth
3c4c460f82 depot: update recipe hashes 2019-06-13 13:40:37 +02:00
Christian Helmuth
2b183f9497 depot: update recipe hashes 2019-05-29 10:20:52 +02:00
Sebastian Sumpf
cec050983a hw: [[fallthrough]] annotations for ARM/RISC-V 
* double checked

issue #3377
 2019-05-29 10:20:52 +02:00
Sebastian Sumpf
d417d26ce8 hw: fix calculation of CPU count on x86_64 
On x86 the CPU count is determined through ACPI's MADT by counting the
local APICs reported there. Some platforms report more APICs
than there are actual CPUs. These might be physically disabled CPUs.
Therefore, a check if the LAPIC is actually physically enabled in
hardware fixes this issue.

Thanks to Alex Boettcher

fixes #3376
 2019-05-29 10:20:52 +02:00
Sebastian Sumpf
5611020f33 hw: fix stack alignment in bootstrap for x86_64 
Fix initial stack pointer alignment for x86_64 in crt0.s startup code of
bootstrap. SysV ABI states that upon function entry (rsp + 8) % 16 = 0.
There, we have to align the stack to 16 bytes before all 'call'
instruction not 8. Otherwise FPU (GP) exception might be raised later on
because of unaligned FPU accesses.

issue #3365
 2019-05-29 10:20:52 +02:00
Sebastian Sumpf
da17f2cbd3 hw: eager FPU switching for x86_64 
Since gcc 8.3.0 generates SSE instructions into kernel code, the
kernel itself may raise FPU exceptions and/or corrupt user level FPU
contexts thereby. Both things are not feasible, and therefore, lazy FPU
switching becomes a no go for base-hw because we cannot avoid FPU
instructions because of the entanglement of base-hw, base, and the tool
chain (libgcc_eh.a).

issue #3365
 2019-05-27 14:53:32 +02:00
Stefan Kalkowski
6d8d6b5552 hw: disable alignment checking at earliest 
Fix #3370
 2019-05-27 14:52:52 +02:00
Sebastian Sumpf
f18285205c hw: enable FPU during CPU startup on x86 
Also disable TS (task switch) flag in cr0 during kernel initialization,
so FPU faults are not raised. This became necessary since GCC lately
aggressively generates FPU instructions at arbitrary places and also at
early kernel-bootstrapping stages.

fixes #3365
 2019-05-27 14:52:52 +02:00
Christian Prochaska
4fc3eca4aa base-hw: fix compile errors with GCC 8.3.0 
Fixes #3326
 2019-05-27 14:46:54 +02:00
Stefan Kalkowski
5c77ebb1fb hw: factor out x86 specific bootinfo 
Ref #3326
 2019-05-27 14:46:54 +02:00
Stefan Kalkowski
054df95ea4 hw: unify board definitions of bootstrap/core 
Ref #3326
 2019-05-27 14:46:54 +02:00
Adrian-Ken Rueegsegger
d131e537e9 Update Muen port 
- Drop unnecessary patch
- Improved build speed/parallelization
- Increased log channel size
- Fix path in base-hw/Muen documentation
 2019-05-27 14:46:53 +02:00