The SMI bus ID for RTL8231 currently defaults to 0, and can be
overridden from the devicetree. However, there is no value check on the
DT-provided value, aside from masking which would only cause value
wrap-around.
Change the driver to always require the "indirect-access-bus-id"
property, as there is no real reason to use 0 as default, and perform a
sanity check on the value when probing. This allows the other parts of
the driver to be simplified a bit.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Set the gpio_chip.base to -1 to use automatic GPIO line indexing.
Setting base to 0 or a positive number is deprecated and should not be
used.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
The RTL8231's gpio_chip.ngpio was set to 36, which is the largest valid
GPIO index. Fix the allowed number of GPIOs by setting ngpio to 37, the
actual line count.
Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Replace magic values with more self-descriptive code now that I start
to understand more about the design of the PHY (and MDIO controller).
Remove one line before reading RTL8214FC internal PHY id which turned
out to be a no-op and can hence safely be removed (confirmed by
INAGAKI Hiroshi[1])
[1]: df8e6be59a (r66890713)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Instead of directly calling SoC-specific functions in order to access
(paged) MII registers or MMD registers, create infrastructure to allow
using the generic phy_*, phy_*_paged and phy_*_mmd functions.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* Add missing Clause-45 write support for rtl931x
* Switch to use helper functions in all Clause-45 access functions to
make the code more readable.
* More meaningful/unified debugging output (dynamic kprintf)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Import commit ("c6af53f038aa3 net: mdio: add helpers to extract clause
45 regad and devad fields") from Linux 5.17 to allow making the MDIO
code in the ethernet driver more readable.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Using the led-set attribute of a port in the dts we allow configuration
of the port leds. Each led-set is being defined in the led-set configuration
of the .dts, giving a specific configuration to steer the port LEDs via a serial
connection.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL8221B PHY is a newer version of the RTL8226, also supporting
2.5GBit Ethernet. It is found with RTL931X devices such as the
EdgeCore ECS4125-10P
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Both the Aquantia AQR113c and the RTL8226 PHYs in the Zyxel XGS1250 and the
Zyxel XGS1210 require special polling configuration settings in the
RTL930X_SMI_10GPHY_POLLING_REGxx_CFG configuration registers. Set them.
Additionally, for RTL 1GBit phys set the RTL930X_SMI_PRVTE_POLLING_CTRL bits
in the poll mask.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
For SFP slots on the RTL9302, the link status is not correctly detected.
Use the link media status instead.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We add the RTL931X sub-target with kernel configuration for
a dual core MIPS InterAptive CPU.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We add HW support routines for the RTL931X SoC family for handling
the Packet Inspection Engine, L2 table handling and STP aging.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We need to store and restore MC memberships in HW when a port joins or
leaves a bridge as well as when it is enabled or disabled, as these
properties should not change in these situations.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
In order to receive STP information at the kernel level, we make sure
that all Bridge Protocol Data Units are copied to the CPU-Port.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Instead of a generic L2 aging configuration function with complex
logic, we implement an individual function for all SoC types.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Add functionality to enable or disable L2 learning offload and port flooding
for RTL83XX.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Adds the DSA API for bridge configuration (flooding, L2 learning,
and aging) offload as found in Linux 5.12 so that we can implement
it in our drivver.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This adds LAG support for all 4 SoC families, including support
ofr the use of different distribution algorithm for the load-
balancing between individual links.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Add the LAG configuration API for DSA as found in Linux 5.12 so that we
can implement it in the dsa driver.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Use setting functions instead of register numbers in order to clean up the code.
Also use enums to define inner/outer VLAN types and the filter type.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The ZyXEL XGS1250-12 Switch is a 11 + 1 port multi-GBit switch with
8 x 1000BaseT, 3 x 1000/2500/5000/10000BaseT Ethernet ports and
1 SFP+ module slot.
Hardware:
- RTL9302B SoC
- Macronix MX25L12833F (16MB flash)
- Nanja NT5CC64M16GP-1 (128MB DDR3 SDRAM)
- RTL8231 GPIO extender to control the port LEDs
- RTL8218D 8x Gigabit PHY
- Aquantia AQR113c 1/2.5/5/10 Gigabit PHYs
- SFP+ 10GBit slot
Power is supplied via a 12V 2A standard barrel connector. At the
right side behind the grid is UART serial connector. A Serial
header can be connected to from the outside of the switch trough
the airvents with a standard 2.54mm header.
Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial
connection is via 115200 baud, 8N1.
A reset button is accessble through a hole in the front panel
At the time of this commit, all ethernet ports work under OpenWRT,
including the various NBaseT modes, however the 10GBit SFP+ slot is not
supported.
Installation
--------------
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* Navigate to 'Management' in the OEM web interface and click on 'Firmware upgrade'
to the left.
* Upload the OpenWrt initramfs image, and wait till the switch reboots.
* Connect to the device through serial and change the U-boot boot command.
> fw_setenv bootcmd 'rtk network on; boota'
* Reboot, scp the sysupgrade image to /tmp, verify the checksum and flash it:
> sysupgrade /tmp/openwrt-realtek-rtl930x-zyxel_xgs1250-12-squashfs-sysupgrade.bin
* Upon reboot, you have a functional OpenWrt installation. Leave the bootcmd
value as is - without 'rtk network on' the switch will fail to initialise
the network.
Web recovery
------------
The XGS1250-12 has a handy web recovery that will load when U-boot does
not find a bootable kernel. In case you would like to trigger the web
recovery manually, partially overwrite the firmware partition with some
zeroes:
# dd if=/dev/zero of=/dev/mtd5 bs=1M count=2
If you have serial connected you'll see U-boot will start the web recovery
and print it's listening on 192.168.1.1, but by default it seems to be on
the OEM default IP for the switch - 192.168.1.3. The web recovery only
listens on HTTP (80) and *not* on 443 (HTTPS) unlike the web UI.
Return to stock
---------------
You can flash the ZyXEL firmware images to return to stock:
# sysupgrade -F -n XGS1250-12_Firmware_V1.00(ABWE.1)C0.bix
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Adds configuration routines for the internal SerDes of the
RTL930X and RTL931X.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Adds a rtl931x_phylink_mac_config for the RTL931X and improve
the handling of the RTL930X phylink configuration. Add separate
handling of the RTL839x since some configurations are different
from the RTL838X.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We were using the PHY-ids (the reg entries in the PHY
sections of the .dts) as the port numbers. Now scan the
ports section in the .dts, and use the actual port numbers,
following the phy-handle to the PHY properties.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
When a port is brought up, read the SDS-id via the phy_device
for a given port and use this to configure the SDS when it
is brought up.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL839X does not have an internal phy and thus does not need to have any
firmware as part of the kernel, especially not firmware for the RTL838X.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Selects the new CEVT timer for Realtek instead of the previous
timer driver. While we are at it, we explicitily state we do
not use the I2C driver of the RTL9300.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL9300 has a broken R4K MIPS timer interrupt, however, the
R4K clocksource works. We replace the RTL9300 timer with a
Clock Event Timer (CEVT), which is VSMP aware and can be instantiated
as part of brining a VSMTP cpu up instead of the R4K CEVT source.
For this we place the RTL9300 CEVT timer in arch/mips/kernel
together with other MIPS CEVT timers, initialize the SoC IRQs
from a modified smp-mt.c and instantiate each timer as part
of the MIPS time setup in arch/mips/include/asm/time.h instead
of the R4K CEVT, similarly as is done by other MIPS CEVT timers.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Various fixes to enable Ethernet on the RTL931X:
- Network start and stop sequence for RTL931X HW
- MDIO access on RTL931X SoC
- Chip initialization
- SerDes setup
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Do not lock the register structure in IRQ context. It is not
necessary and leads to lockups under SMP load.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Rename the SoC-specific rtl838x_reg structure in the Ethernet
driver to avoid confusion with the structure of the same name
in the DSA driver. New name is: rtl838x_eth_reg
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Setting bits 20 and 23 in a u16 is obviously wrong.
According to https://www.svanheule.net/realtek/cypress/cputag
cpu_tag[2] starts at bit 48 in the cpu-tag structure, so
bit 43 is bit 5 in cpu_tag[2] and bit 40 is bit 8 in
cpu_tag[2].
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Set CONFIG_FORCE_MAX_ZONEORDER setting to 13 to allow larger
contiguous memory allocation for the DMA of the Ethernet
driver. Increase the number of entries in the RX ring
to 300 making use of the larger DMA region now possible for
receiveing packets.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The GS1900-48 is a 48 + 2 port Gigabit L2 switch with 48 gigabit ports.
Hardware:
RTL8393M SoC
Macronix MX25l12805D (16MB flash)
128MB RAM
6 * RTL8218B external PHY
2 * RTL8231 GPIO extenders to control the port LEDs, system LED and
Reset button
2 Uplink ports are SFP cages which support 1000 Base-X mini GBIC modules.
Power is supplied via a 230 volt mains connector.
The board has a hard reset switch SW1, which is is not reachable from the outside.
J4 provides a 12V RS232 serial connector which is connected through U8 to
the 3.3V UART of the RTL8393. Conversion is done by U8, a SIPEX 3232EC.
To connect to the UART, wires can be soldered to R603 (TX) and R602 (RX).
Installation:
Install the squashfs image via Realtek's original Web-Interface.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Update the IRQ configuration to work with the new rtl-intc controller.
Also change all KSEG1 addresses in reg = <> of the devics to physical
addresses.
Use the new gpio-otto controller instead of the legacy driver.
Also remove the memory node as this is better put into a device .dts.
Also remove the RTL8231 GPIO controller node from this base file
since the chip might not be found in all Realtek RTL839x devices.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Replace the interrupt controller node with the new realtek,rtl-intc
node and change all device interrupts to use the 2 field notation:
interrupts = <[SoC IRQ] [Index to MIPS IRQ]>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
In order to support VSMP, enable support for both VPEs
of the RTL839X and RTL930X SoCs in the irq-realtek-rtl
driver. Add support for IRQ affinity setting.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
In order for the Platform includes to be available on
all sub-targets, make them dependent on CONFIG_RTL83XX.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL838X SoCs do not use Aquantia PHYs, remove this.
Also the RTL838X uses a high resolution R4K timer.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Creates RTL83XX as a basic kernel config parameter for the
RTL838X, RTL839x, RTL930X and RTL931X platforms with respective
configurations for the SoCs, which are introduced in addition.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Create the RTL838x specific Makefiles. Move CPU-type into
rtl838x.mk as this is specifc to that platform. Add
rtl838x subtarget into main Makefile.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
mv generic/target.mk to rtl838x/target.mk in order to create
an initial makefile for the rtl838x sub-architecture
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The EEPROMs on SFP modules are compatible both to I2C as well
as SMBus. However, the kernel so far only supports I2C
access. We add SMBus access routines, because the I2C driver
for the RTL9300 HW only supports that protocol. At the same
time we disable I2C access to PHYs on SFP modules as otherwise
detection of any SFP module would fail. This is not in any
way problematic at this point in time since the RTL93XX
platform so far does not support PHYs on SFP modules.
The patches are copied and rebased version of:
https://bootlin.com/blog/sfp-modules-on-a-board-running-linux/
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL9300/RTL9310 I2C controllers have support for 2 independent I2C
masters, each with a fixed SCL pin, that cannot be changed. Each of these
masters can use 8 (RTL9300) or 16 (RTL9310) different pins for SDA.
This multiplexer directly controls the two masters and their shared
IO configuration registers to allow multiplexing between any of these
busses. The two masters cannot be used in parallel as the multiplex
is protected by a standard multiplex lock.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This adds support for the RTL9300 and RTL9310 I2C controller.
The controller implements the SMBus protocol for SMBus transfers
over an I2C bus. The driver supports selecting one of the 2 possible
SCL pins and any of the 8 possible SDA pins. Bus speeds of
100kHz (standard speed) and 400kHz (high speed I2C) are supported.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This patch removes support for the legacy GPIO driver, since now
the gpio-otto driver can be used on all platforms
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We add support for the RTL930X and RTL931X architectures
in the gpio-realtek-otto.c driver.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Drop patches and files for Linux 5.4 now that we've been using 5.10
for a while and support for Linux 5.4 has gone out-of-sync.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The bit position mask was accidentally made too wide, overlapping with the LSB
from the byte position mask. This caused ECC calculation to fail for odd bytes
Signed-off-by: Chad Monroe <chad.monroe@smartrg.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
flowtable->net was initialized too late, and this could be triggered even
without hardware offload support on the device
Signed-off-by: Felix Fietkau <nbd@nbd.name>
It's reported that current memory detection code occasionally detects
larger memory under some bootloaders.
Current memory detection code tests whether address space wraps around
on KSEG0, which is unreliable because it's cached.
Rewrite memory size detection to perform the same test on KSEG1 instead.
While at it, this patch also does the following two things:
1. use a fixed pattern instead of a random function pointer as the magic
value.
2. add an additional memory write and a second comparison as part of the
test to prevent possible smaller memory detection result due to
leftover values in memory.
Fixes: 6d91ddf517 ("ramips: mt7621: add support for memory detection")
Reported-by: Rui Salvaterra <rsalvaterra@gmail.com>
Tested-by: Rui Salvaterra <rsalvaterra@gmail.com>
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
The issue of EAP frames sent to group address (or the wrong address) has been
addressed in mac80211, so this hack is no longer needed
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This caches flows between MAC addresses on separate ports, including their VLAN
in order to bypass the normal bridge forwarding code.
In my test on MT7622, this reduces LAN->WLAN bridging CPU usage by 6-10%,
potentially even more on weaker platforms
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Had to update generic defconfig (make kernel_menuconfig CONFIG_TARGET=generic)
for this bump, but since that only modifies the target defined in .config,
and since that target also needed to be updated for unrelated reasons, manually
propagated the newly added symbol to the generic config.
Removed upstreamed:
pending-5.10/860-Revert-ASoC-mediatek-Check-for-error-clk-pointer.patch[1]
All other patches automatically rebased.
1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.99&id=080f371d984e8039c66db87f3c54804b0d172329
Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200
Signed-off-by: John Audia <graysky@archlinux.us>
The locations of MAC addresses in mtd for LAN/WAN on ELECOM WRC-2533GS2
are changed from the other WRC-GS/GST devices with 2x PCIe. So move the
related configurations in mt7621_elecom_wrc-gs-2pci.dtsi to dts of each
model.
- WRC-1750GS
- WRC-1750GSV
- WRC-1750GST2
- WRC-1900GST
- WRC-2533GST
- WRC-2533GST2
-> LAN: 0xE000, WAN: 0xE006
- WRC-2533GS2
-> LAN: 0xFFF4, WAN: 0xFFFA
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Reported MAC addresses:
| interface | MAC address | source | comment
|-----------|-------------------|----------------|---------
| LAN | 90:xx:xx:18:xx:1F | | [1]
| WAN | 90:xx:xx:18:xx:1D | |
| WLAN 2G | 92:xx:xx:48:xx:1C | |
| WLAN 5G | 90:xx:xx:18:xx:1C | factory 0x4 |
| | 90:xx:xx:18:xx:1C | config ethaddr |
[1] Used in this patch as WLAN 2G MAC address with the local bit set
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
ipTIME AX2004M is an 802.11ax (Wi-Fi 6) router, based on MediaTek
MT7621A.
Specifications:
* SoC: MT7621A
* RAM: 256 MiB
* Flash: NAND 128 MiB
* Wi-Fi:
* MT7915D: 2.4/5 GHz (DBDC)
* Ethernet: 5x 1GbE
* Switch: SoC built-in
* USB: 1x 3.0
* UART: J4 (115200 baud)
* Pinout: [3V3] (TXD) (RXD) (GND)
MAC addresses:
| interface | MAC address | source | comment
|-----------|-------------------|----------------|---------
| LAN | 58:xx:xx:00:xx:9B | | [1]
| WAN | 58:xx:xx:00:xx:99 | |
| WLAN 2G | 58:xx:xx:00:xx:98 | factory 0x4 |
| WLAN 5G | 5A:xx:xx:40:xx:98 | |
| | 58:xx:xx:00:xx:98 | config ethaddr |
[1] Used in this patch as WLAN 5G MAC address with the local bit set
Load addresses:
* stock
* 0x80010000: FIT image
* 0x81001000: kernel image -> entry
* OpenWrt
* 0x80010000: FIT image
* 0x82000000: uncompressed kernel+relocate image
* 0x80001000: relocated kernel image -> entry
Notes:
* This device has a dual-boot partition scheme, but this firmware works
only on boot partition 1. The stock web interface will flash only on the
inactive boot partition, but the recovery web page will always flash on
boot partition 1.
Installation via recovery mode:
1. Press reset button, power up the device, wait >10s for CPU LED
to stop blinking.
2. Upload recovery image through the recovery web page at 192.168.0.1.
Revert to stock firmware:
1. Install stock image via recovery mode.
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
Turns out the MT7531 switch IRQ line is connected to GPIO#53 just like
on the BPi-R64, so this seems to be part of the reference design and
will probably apply to most MT7622+MT7531 boards.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Now that we support link-state-change interrupts, wire up MT7531 IRQ
line which is connected to GPIO#53 according to the schematics [1].
As a result, PHY state no longer needs to be polled on that board.
[1]: https://forum.banana-pi.org/t/bpi-r64-mt7622-schematic-diagram-public/10118
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Support MT7530 PHY link change interrupts, and enable for MT7621.
For external MT7530, a GPIO IRQ line is required, which is
board-specific, so it should be added to each DTS. In case the
interrupt-controller property is missing, it will fall back to
polling mode.
Signed-off-by: DENG Qingfang <dqfext@gmail.com>
Add support for MediaTek Gigabit Ethernet PHYs found in MT7530 and
MT7531. Fix some link up/down issues.
The errornous check for the PHY mode which broke things with MT7531
has been removed as suggested by patch
net: phy: mediatek: remove PHY mode check on MT7531
As a result, things are working fine now on MT7622+MT7531 as well.
Signed-off-by: DENG Qingfang <dqfext@gmail.com>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
The kernel configuration allows us to select a default qdisc. Let's do this for
5.10 (as 5.4 is on its way out) and get rid of the hacky patch we've been
carrying.
Acked-by: Jo-Philipp Wich <jo@mein.io>
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
Commit f4a79148f8 ("ramips: add support for ipTIME AX2004M") was
reverted due to KERNEL_LOADADDR leakage, and it seems the problem can be
mitigated by moving the variable definition into Device/Default. By this,
KERNEL_LOADADDR redefined in a device recipe will not be leaked into the
subsequent device recipes anymore and thus will remain as a per-device
variable.
Ref: cd6a6e3030 ("Revert "ramips: add support for ipTIME AX2004M"")
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
Increase the available flash memory size in Netgear R7800
by repurposing the unused "netgear" partition that is
located after the firmware partition.
Available flash space for kernel+rootfs+overlay increases
by 68 MB from 32 MB to 100 MB.
In a typical build, overlay space increases from 15 to 85,
increasing the package installation possibilities greatly.
Reverting to the OEM firmware is still possible, as the OEM
firmware contains logic to initialise the "netgear" partition
if its contents do not match expectations. In OEM firmware,
"netgear" contains 6 UBI sub-partitions that are defined in
/etc/netgear.cfg and initialisation is done by /etc/preinit
This is based on fb8a578aa7
Signed-off-by: Mike Lothian <mike@fireburn.co.uk>
Xiaomi Mi Router CR6606 is a Wi-Fi6 AX1800 Router with 4 GbE Ports.
Alongside the general model, it has three carrier customized models:
CR6606 (China Unicom), CR6608 (China Mobile), CR6609 (China Telecom)
Specifications:
- SoC: MediaTek MT7621AT
- RAM: 256MB DDR3 (ESMT M15T2G16128A)
- Flash: 128MB NAND (ESMT F59L1G81MB)
- Ethernet: 1000Base-T x4 (MT7530 SoC)
- WLAN: 2x2 2.4GHz 574Mbps + 2x2 5GHz 1201Mbps (MT7905DAN + MT7975DN)
- LEDs: System (Blue, Yellow), Internet (Blue, Yellow)
- Buttons: Reset, WPS
- UART: through-hole on PCB ([VCC 3.3v](RX)(GND)(TX) 115200, 8n1)
- Power: 12VDC, 1A
Jailbreak Notes:
1. Get shell access.
1.1. Get yourself a wireless router that runs OpenWrt already.
1.2. On the OpenWrt router:
1.2.1. Access its console.
1.2.2. Create and edit
/usr/lib/lua/luci/controller/admin/xqsystem.lua
with the following code (exclude backquotes and line no.):
```
1 module("luci.controller.admin.xqsystem", package.seeall)
2
3 function index()
4 local page = node("api")
5 page.target = firstchild()
6 page.title = ("")
7 page.order = 100
8 page.index = true
9 page = node("api","xqsystem")
10 page.target = firstchild()
11 page.title = ("")
12 page.order = 100
13 page.index = true
14 entry({"api", "xqsystem", "token"}, call("getToken"), (""),
103, 0x08)
15 end
16
17 local LuciHttp = require("luci.http")
18
19 function getToken()
20 local result = {}
21 result["code"] = 0
22 result["token"] = "; nvram set ssh_en=1; nvram commit; sed -i
's/channel=.*/channel=\"debug\"/g' /etc/init.d/dropbear; /etc/init.d/drop
bear start;"
23 LuciHttp.write_json(result)
24 end
```
1.2.3. Browse http://{OWRT_ADDR}/cgi-bin/luci/api/xqsystem/token
It should give you a respond like this:
{"code":0,"token":"; nvram set ssh_en=1; nvram commit; ..."}
If so, continue; Otherwise, check the file, reboot the rout-
er, try again.
1.2.4. Set wireless network interface's IP to 169.254.31.1, turn
off DHCP of wireless interface's zone.
1.2.5. Connect to the router wirelessly, manually set your access
device's IP to 169.254.31.3, make sure
http://169.254.31.1/cgi-bin/luci/api/xqsystem/token
still have a similar result as 1.2.3 shows.
1.3. On the Xiaomi CR660x:
1.3.1. Login to the web interface. Your would be directed to a
page with URL like this:
http://{ROUTER_ADDR}/cgi-bin/luci/;stok={STOK}/web/home#r-
outer
1.3.2. Browse this URL with {STOK} from 1.3.1, {WIFI_NAME}
{PASSWORD} be your OpenWrt router's SSID and password:
http://{MIROUTER_ADDR}/cgi-bin/luci/;stok={STOK}/api/misy-
stem/extendwifi_connect?ssid={WIFI_NAME}&password={PASSWO-
RD}
It should return 0.
1.3.3. Browse this URL with {STOK} from 1.3.1:
http://{MIROUTER_ADDR}/cgi-bin/luci/;stok={STOK}/api/xqsy-
stem/oneclick_get_remote_token?username=xxx&password=xxx&-
nonce=xxx
1.4. Before rebooting, you can now access your CR660x via SSH.
For CR6606, you can calculate your root password by this project:
https://github.com/wfjsw/xiaoqiang-root-password, or at
https://www.oxygen7.cn/miwifi.
The root password for carrier-specific models should be the admi-
nistration password or the default login password on the label.
It is also feasible to change the root password at the same time
by modifying the script from step 1.2.2.
You can treat OpenWrt Router however you like from this point as
long as you don't mind go through this again if you have to expl-
oit it again. If you do have to and left your OpenWrt router unt-
ouched, start from 1.3.
2. There's no official binary firmware available, and if you lose the
content of your flash, no one except Xiaomi can help you.
Dump these partitions in case you need them:
"Bootloader" "Nvram" "Bdata" "crash" "crash_log"
"firmware" "firmware1" "overlay" "obr"
Find the corespond block device from /proc/mtd
Read from read-only block device to avoid misoperation.
It's recommended to use /tmp/syslogbackup/ as destination, since files
would be available at http://{ROUTER_ADDR}/backup/log/YOUR_DUMP
Keep an eye on memory usage though.
3. Since UART access is locked ootb, you should get UART access by modify
uboot env. Otherwise, your router may become bricked.
Excute these in stock firmware shell:
a. nvram set boot_wait=on
b. nvram set bootdelay=3
c. nvram commit
Or in OpenWrt:
a. opkg update && opkg install kmod-mtd-rw
b. insmod mtd-rw i_want_a_brick=1
c. fw_setenv boot_wait on
d. fw_setenv bootdelay 3
e. rmmod mtd-rw
Migrate to OpenWrt:
1. Transfer squashfs-firmware.bin to the router.
2. nvram set flag_try_sys1_failed=0
3. nvram set flag_try_sys2_failed=1
4. nvram commit
5. mtd -r write /path/to/image/squashfs-firmware.bin firmware
Additional Info:
1. CR660x series routers has a different nand layout compared to other
Xiaomi nand devices.
2. This router has a relatively fresh uboot (2018.09) compared to other
Xiaomi devices, and it is capable of booting fit image firmware.
Unfortunately, no successful attempt of booting OpenWrt fit image
were made so far. The cause is still yet to be known. For now, we use
legacy image instead.
Signed-off-by: Raymond Wang <infiwang@pm.me>
The MikroTik LHG 5 series (product codes RBLHG-5nD, RBLHG-5HPnD and
RBLHG-5HPnD-XL) devices are an outdoor 5GHz CPE with a 24.5dBi or 27dBi
integrated antenna built around the Atheros AR9344 SoC.
It is very similar to the SXT Lite5 series which this patch is based
upon.
Specifications:
- SoC: Atheros AR9344
- RAM: 64 MB
- Storage: 16 MB SPI NOR
- Wireless: Atheros AR9340 (SoC) 802.11a/n 2x2:2
- Ethernet: Atheros AR8229 switch (SoC), 1x 10/100 port,
8-32 Vdc PoE in
- 8 user-controllable LEDs:
- 1x power (blue)
- 1x user (white)
- 1x ethernet (green)
- 5x rssi (green)
See https://mikrotik.com/product/RBLHG-5nD for more details.
Notes:
The device was already supported in the ar71xx target.
Flashing:
TFTP boot initramfs image and then perform a sysupgrade. Follow common
MikroTik procedure as in https://openwrt.org/toh/mikrotik/common.
Signed-off-by: Jakob Riepler <jakob+openwrt@chaosfield.at>
Hardware
--------
SoC: QCN5502
Flash: 16 MiB
RAM: 128 MiB
Ethernet: 1 gigabit port
Wireless No1: QCN5502 on-chip 2.4GHz 4x4
Wireless No2: QCA9984 pcie 5GHz 4x4
USB: none
Installation
------------
Flash the factory image using the stock web interface or TFTP the
factory image to the bootloader.
What works
----------
- LEDs
- Ethernet port
- 5GHz wifi (QCA9984 pcie)
What doesn't work
-----------------
- 2.4GHz wifi (QCN5502 on-chip)
(I was not able to make this work, probably because ath9k requires
some changes to support QCN5502.)
Signed-off-by: Wenli Looi <wlooi@ucalgary.ca>
Based on wikidevi, QCN5502 is a "Dragonfly" like QCA9561 and QCA9563.
Treating it as QCA956x seems to work.
Signed-off-by: Wenli Looi <wlooi@ucalgary.ca>
Specifications:
- AR9344 SoC, 8 MB nor flash, 64 MB DDR2 RAM
- 2x2 9dBi antenna, wifi 2.4Ghz 300Mbps
- 4x Ethernet LAN 10/100, 1x Ethernet WAN 10/100
- 1x WAN, 4x LAN, Wifi, PWR, WPS, SYSTEM Leds
- Reset/WPS button
- Serial UART at J4 onboard: 3.3v GND RX TX, 1152008N1
MAC addresses as verified by OEM firmware:
vendor OpenWrt address
LAN eth0 label
WAN eth1 label + 1
WLAN phy0 label
The label MAC address was found in u-boot 0x1fc00.
Installation:
To install openwrt,
- set the device's SSID to each of the following lines,
making sure to include the backticks.
- set the ssid and click save between each line.
`echo "httpd -k"> /tmp/s`
`echo "sleep 10">> /tmp/s`
`echo "httpd -r&">> /tmp/s`
`echo "sleep 10">> /tmp/s`
`echo "httpd -k">> /tmp/s`
`echo "sleep 10">> /tmp/s`
`echo "httpd -f">> /tmp/s`
`sh /tmp/s`
- Now, wait 60 sec.
- After the reboot sequence, the router may have fallen back to
its default IP address with the default credentials (admin:admin).
- Log in to the web interface and go the the firmware upload page.
Select "openwrt-ath79-generic-tplink_tl-wr841hp-v2-squashfs-factory.bin"
and you're done : the system now accepts the openwrt.
Forum support topic:
https://forum.openwrt.org/t/support-for-tplink-tl-wr841hp-v2/69445/
Signed-off-by: Saiful Islam <si87868@gmail.com>
The recent device-tree modification that added pre-cal
nvmem-cells pushed the device's kernel+dtb over the
allotted 3072k KERNEL_SIZE.
> WARNING: Image file tplink_vr2600v-uImage is too big: 3147214 > 3145728
There was a previous kernel partition size upgrade:
commit 0c967d92b3 ("ipq806x: increase kernel partition size for the TP-Link Archer VR2600v")
It has been seemingly upgraded from a 2048k KERNEL_SIZE in the past.
The commit talks about using the MTD_SPLIT_TPLINK_FW. But looking at
the image make recipe, there is no code that adds a TPLINK header.
So instead the board will use "denx,umimage". This requires
MTD_SPLIT_UIMAGE_FW, but this is present thanks to some NEC devices.
(Maybe the MTD_CONFIG_ARGS can be removed as well? But it could be
there because of the padding at the beginning. This needs testing.)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
This reverts commit 8b4cba53a9.
This broke the mt7530 on Linksys e8450 (mt7622) for me.
[ 1.312943] mt7530 mdio-bus:00 lan1 (uninitialized): failed to connect to PHY: -EINVAL
[ 1.320890] mt7530 mdio-bus:00 lan1 (uninitialized): error -22 setting up PHY for tree 0, switch 0, port 0
[ 1.331163] mt7530 mdio-bus:00 lan2 (uninitialized): failed to connect to PHY: -EINVAL
[ 1.339085] mt7530 mdio-bus:00 lan2 (uninitialized): error -22 setting up PHY for tree 0, switch 0, port 1
[ 1.349321] mt7530 mdio-bus:00 lan3 (uninitialized): failed to connect to PHY: -EINVAL
[ 1.357241] mt7530 mdio-bus:00 lan3 (uninitialized): error -22 setting up PHY for tree 0, switch 0, port 2
[ 1.367452] mt7530 mdio-bus:00 lan4 (uninitialized): failed to connect to PHY: -EINVAL
[ 1.375367] mt7530 mdio-bus:00 lan4 (uninitialized): error -22 setting up PHY for tree 0, switch 0, port 3
[ 1.385750] mt7530 mdio-bus:00 wan (uninitialized): failed to connect to PHY: -EINVAL
[ 1.393575] mt7530 mdio-bus:00 wan (uninitialized): error -22 setting up PHY for tree 0, switch 0, port 4
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This reverts commit 3f4301e123.
This broke the mt7530 on Linksys e8450 (mt7622) for me.
[ 1.300554] mt7530 mdio-bus:00: no interrupt support
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Support MT7530 PHY link change interrupts, and enable for MT7621.
Signed-off-by: DENG Qingfang <dqfext@gmail.com>
Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Add support for MediaTek Gigabit Ethernet PHYs found in MT7530.
Fix some link up/down issues.
Signed-off-by: DENG Qingfang <dqfext@gmail.com>
Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Use hardware to forward multicast traffic instead of trapping to the
host.
Signed-off-by: DENG Qingfang <dqfext@gmail.com>
Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
