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https://github.com/openwrt/openwrt.git
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realtek: Fix RTL931X Ethernet driver
Various fixes to enable Ethernet on the RTL931X: - Network start and stop sequence for RTL931X HW - MDIO access on RTL931X SoC - Chip initialization - SerDes setup Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This commit is contained in:
Birger Koblitz
Daniel Golle
parent
1b1f05f682
commit
0536c582e6
@ -693,7 +693,7 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
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sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); // Disabled on RTL8380
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if (priv->family_id == RTL8390_FAMILY_ID)
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sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
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if (priv->family_id == RTL9300_FAMILY_ID) {
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if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
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for (i = 0; i < priv->rxrings; i++) {
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pos = (i % 3) * 10;
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sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));
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@ -806,8 +806,15 @@ static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)
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/* Restart TX/RX to CPU port, enable CRC checking */
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sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
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sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
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sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
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if (priv->family_id == RTL9300_FAMILY_ID)
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sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
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else
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sw_w32_mask(0, BIT(priv->cpu_port), RTL931X_L2_UNKN_UC_FLD_PMSK);
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if (priv->family_id == RTL9300_FAMILY_ID)
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sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
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else
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sw_w32(0x2a1d, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
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}
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static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)
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@ -924,10 +931,20 @@ static int rtl838x_eth_open(struct net_device *ndev)
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sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL);
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break;
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case RTL9310_FAMILY_ID:
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rtl93xx_hw_en_rxtx(priv);
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// Trap MLD and IGMP messages to CPU_PORT
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sw_w32((0x2 << 3) | 0x2, RTL931X_VLAN_APP_PKT_CTRL);
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// Disable External CPU access to switch, clear EXT_CPU_EN
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sw_w32_mask(BIT(2), 0, RTL931X_MAC_L2_GLOBAL_CTRL2);
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// Set PCIE_PWR_DOWN
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sw_w32_mask(0, BIT(1), RTL931X_PS_SOC_CTRL);
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break;
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}
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}
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netif_tx_start_all_queues(ndev);
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@ -976,8 +993,10 @@ static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
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/* CPU-Port: Link down */
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if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
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sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
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else
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else if (priv->family_id == RTL9300_FAMILY_ID)
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sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
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else if (priv->family_id == RTL9310_FAMILY_ID)
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sw_w32_mask(BIT(0) | BIT(9), 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
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mdelay(100);
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/* Disable all TX/RX interrupts */
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@ -1465,6 +1484,15 @@ static void rtl838x_mac_pcs_get_state(struct phylink_config *config,
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case 2:
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state->speed = SPEED_1000;
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break;
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case 5:
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state->speed = SPEED_2500;
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break;
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case 6:
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state->speed = SPEED_5000;
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break;
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case 4:
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state->speed = SPEED_10000;
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break;
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default:
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state->speed = SPEED_UNKNOWN;
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break;
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@ -1554,12 +1582,16 @@ static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
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if (priv->family_id == 0x8390)
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return rtl8390_init_mac(priv);
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// At present we do not know how to set up EEE on any other SoC than RTL8380
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if (priv->family_id != 0x8380)
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return 0;
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pr_info("%s\n", __func__);
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/* fix timer for EEE */
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sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
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sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
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/* Init VLAN */
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/* Init VLAN. TODO: Understand what is being done, here */
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if (priv->id == 0x8382) {
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for (i = 0; i <= 28; i++)
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sw_w32(0, 0xd57c + i * 0x80);
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@ -1622,32 +1654,50 @@ static int rtl930x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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u32 val;
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int err;
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struct rtl838x_eth_priv *priv = bus->priv;
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// TODO: These are hard-coded for the 2 Fibre Ports of the XGS1210
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if (mii_id >= 26 && mii_id <= 27)
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return rtl930x_read_sds_phy(mii_id - 18, 0, regnum);
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if (priv->phy_is_internal[mii_id])
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return rtl930x_read_sds_phy(priv->sds_id[mii_id], 0, regnum);
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if (regnum & MII_ADDR_C45) {
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regnum &= ~MII_ADDR_C45;
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err = rtl930x_read_mmd_phy(mii_id, regnum >> 16, regnum & 0xffff, &val);
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pr_debug("MMD: %d register %d read %x, err %d\n", mii_id, regnum & 0xffff, val, err);
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} else {
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err = rtl930x_read_phy(mii_id, 0, regnum, &val);
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pr_debug("PHY: %d register %d read %x, err %d\n", mii_id, regnum, val, err);
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}
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if (err)
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return err;
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return val;
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}
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static int rtl931x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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u32 val;
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int err;
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// struct rtl838x_eth_priv *priv = bus->priv;
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int err, v;
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struct rtl838x_eth_priv *priv = bus->priv;
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// if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
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// return rtl839x_read_sds_phy(mii_id, regnum);
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pr_debug("%s: In here, port %d\n", __func__, mii_id);
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if (priv->sds_id[mii_id] >= 0 && mii_id >= 52) {
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v = rtl931x_read_sds_phy(priv->sds_id[mii_id], 0, regnum);
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if (v < 0) {
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err = v;
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} else {
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err = 0;
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val = v;
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}
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} else {
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if (regnum & MII_ADDR_C45) {
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regnum &= ~MII_ADDR_C45;
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err = rtl931x_read_mmd_phy(mii_id, regnum >> 16, regnum & 0xffff, &val);
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} else {
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err = rtl931x_read_phy(mii_id, 0, regnum, &val);
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}
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pr_debug("%s: phy %d, register %d value %x\n", __func__, mii_id, regnum, val);
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}
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err = rtl931x_read_phy(mii_id, 0, regnum, &val);
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if (err)
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return err;
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return val;
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@ -1682,10 +1732,11 @@ static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
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static int rtl930x_mdio_write(struct mii_bus *bus, int mii_id,
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int regnum, u16 value)
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{
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// struct rtl838x_eth_priv *priv = bus->priv;
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struct rtl838x_eth_priv *priv = bus->priv;
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if (priv->sds_id[mii_id] >= 0)
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return rtl930x_write_sds_phy(priv->sds_id[mii_id], 0, regnum, value);
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// if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
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// return rtl839x_write_sds_phy(mii_id, regnum, value);
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if (regnum & MII_ADDR_C45) {
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regnum &= ~MII_ADDR_C45;
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return rtl930x_write_mmd_phy(mii_id, regnum >> 16, regnum & 0xffff, value);
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@ -1697,10 +1748,10 @@ static int rtl930x_mdio_write(struct mii_bus *bus, int mii_id,
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static int rtl931x_mdio_write(struct mii_bus *bus, int mii_id,
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int regnum, u16 value)
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{
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// struct rtl838x_eth_priv *priv = bus->priv;
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struct rtl838x_eth_priv *priv = bus->priv;
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// if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
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// return rtl839x_write_sds_phy(mii_id, regnum, value);
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if (priv->sds_id[mii_id] >= 0)
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return rtl931x_write_sds_phy(priv->sds_id[mii_id], 0, regnum, value);
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return rtl931x_write_phy(mii_id, 0, regnum, value);
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}
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@ -1784,6 +1835,101 @@ static int rtl930x_mdio_reset(struct mii_bus *bus)
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return 0;
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}
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static int rtl931x_mdio_reset(struct mii_bus *bus)
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{
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int i;
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int pos;
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struct rtl838x_eth_priv *priv = bus->priv;
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u32 c45_mask = 0;
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u32 poll_sel[4];
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u32 poll_ctrl = 0;
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bool mdc_on[4];
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pr_info("%s called\n", __func__);
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// Disable port polling for configuration purposes
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sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
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sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
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msleep(100);
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mdc_on[0] = mdc_on[1] = mdc_on[2] = mdc_on[3] = false;
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// Mapping of port to phy-addresses on an SMI bus
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poll_sel[0] = poll_sel[1] = poll_sel[2] = poll_sel[3] = 0;
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for (i = 0; i < 56; i++) {
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pos = (i % 6) * 5;
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sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos, RTL931X_SMI_PORT_ADDR + (i / 6) * 4);
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pos = (i * 2) % 32;
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poll_sel[i / 16] |= priv->smi_bus[i] << pos;
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poll_ctrl |= BIT(20 + priv->smi_bus[i]);
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mdc_on[priv->smi_bus[i]] = true;
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}
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// Configure which SMI bus is behind which port number
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for (i = 0; i < 4; i++) {
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pr_info("poll sel %d, %08x\n", i, poll_sel[i]);
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sw_w32(poll_sel[i], RTL931X_SMI_PORT_POLLING_SEL + (i * 4));
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}
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// Configure which SMI busses
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pr_info("%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
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pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
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for (i = 0; i < 4; i++) {
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// bus is polled in c45
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if (priv->smi_bus_isc45[i])
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c45_mask |= 0x2 << (i * 2); // Std. C45, non-standard is 0x3
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// Enable bus access via MDC
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if (mdc_on[i])
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sw_w32_mask(0, BIT(9 + i), RTL931X_MAC_L2_GLOBAL_CTRL2);
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}
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pr_info("%s: RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
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pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
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/* We have a 10G PHY enable polling
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sw_w32(0x01010000, RTL931X_SMI_10GPHY_POLLING_SEL2);
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sw_w32(0x01E7C400, RTL931X_SMI_10GPHY_POLLING_SEL3);
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sw_w32(0x01E7E820, RTL931X_SMI_10GPHY_POLLING_SEL4);
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*/
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sw_w32_mask(0xff, c45_mask, RTL931X_SMI_GLB_CTRL1);
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return 0;
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}
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static int rtl931x_chip_init(struct rtl838x_eth_priv *priv)
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{
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pr_info("In %s\n", __func__);
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// Initialize Encapsulation memory and wait until finished
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sw_w32(0x1, RTL931X_MEM_ENCAP_INIT);
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do { } while (sw_r32(RTL931X_MEM_ENCAP_INIT) & 1);
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pr_info("%s: init ENCAP done\n", __func__);
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// Initialize Managemen Information Base memory and wait until finished
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sw_w32(0x1, RTL931X_MEM_MIB_INIT);
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do { } while (sw_r32(RTL931X_MEM_MIB_INIT) & 1);
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pr_info("%s: init MIB done\n", __func__);
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// Initialize ACL (PIE) memory and wait until finished
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sw_w32(0x1, RTL931X_MEM_ACL_INIT);
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do { } while (sw_r32(RTL931X_MEM_ACL_INIT) & 1);
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pr_info("%s: init ACL done\n", __func__);
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// Initialize ALE memory and wait until finished
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sw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0);
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do { } while (sw_r32(RTL931X_MEM_ALE_INIT_0));
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sw_w32(0x7F, RTL931X_MEM_ALE_INIT_1);
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sw_w32(0x7ff, RTL931X_MEM_ALE_INIT_2);
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do { } while (sw_r32(RTL931X_MEM_ALE_INIT_2) & 0x7ff);
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pr_info("%s: init ALE done\n", __func__);
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// Enable ESD auto recovery
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sw_w32(0x1, RTL931X_MDX_CTRL_RSVD);
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// Init SPI, is this for thermal control or what?
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sw_w32_mask(0x7 << 11, 0x2 << 11, RTL931X_SPI_CTRL0);
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return 0;
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}
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static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
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{
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struct device_node *mii_np, *dn;
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@ -1870,7 +2016,6 @@ static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
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if (of_property_read_bool(dn, "phy-is-integrated")) {
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priv->phy_is_internal[pn] = true;
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}
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}
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snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
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@ -2108,6 +2253,7 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev)
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priv->cpu_port = RTL931X_CPU_PORT;
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priv->r = &rtl931x_reg;
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dev->netdev_ops = &rtl931x_eth_netdev_ops;
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rtl931x_chip_init(priv);
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break;
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default:
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pr_err("Unknown SoC family\n");
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