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realtek: Improve MAC config handling for all SoCs
Adds a rtl931x_phylink_mac_config for the RTL931X and improve the handling of the RTL930X phylink configuration. Add separate handling of the RTL839x since some configurations are different from the RTL838X. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This commit is contained in:
Birger Koblitz
Daniel Golle
parent
c7cc4e95a5
commit
51c8f76612
@ -38,7 +38,7 @@ static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
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v |= BIT_ULL(i);
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}
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pr_debug("%s: %16llx\n", __func__, v);
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pr_info("%s: %16llx\n", __func__, v);
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priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
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/* PHY update complete, there is no global PHY polling enable bit on the 9300 */
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@ -131,6 +131,11 @@ static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
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info.hash_mc_fid = false; // Do the same for Multicast packets
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info.profile_id = 0; // Use default Vlan Profile 0
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info.tagged_ports = 0; // Initially no port members
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if (priv->family_id == RTL9310_FAMILY_ID) {
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info.if_id = 0;
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info.multicast_grp_mask = 0;
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info.l2_tunnel_list_id = -1;
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}
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// Initialize all vlans 0-4095
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for (i = 0; i < MAX_VLANS; i ++)
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@ -195,7 +200,7 @@ static int rtl83xx_setup(struct dsa_switch *ds)
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return 0;
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}
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static int rtl930x_setup(struct dsa_switch *ds)
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static int rtl93xx_setup(struct dsa_switch *ds)
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{
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int i;
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struct rtl838x_switch_priv *priv = ds->priv;
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@ -203,11 +208,14 @@ static int rtl930x_setup(struct dsa_switch *ds)
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pr_info("%s called\n", __func__);
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// Enable CSTI STP mode
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// sw_w32(1, RTL930X_ST_CTRL);
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/* Disable MAC polling the PHY so that we can start configuration */
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sw_w32(0, RTL930X_SMI_POLL_CTRL);
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if (priv->family_id == RTL9300_FAMILY_ID)
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sw_w32(0, RTL930X_SMI_POLL_CTRL);
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if (priv->family_id == RTL9310_FAMILY_ID) {
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sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
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sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
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}
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// Disable all ports except CPU port
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for (i = 0; i < ds->num_ports; i++)
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@ -322,6 +330,7 @@ static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
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unsigned long *supported,
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struct phylink_link_state *state)
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{
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struct rtl838x_switch_priv *priv = ds->priv;
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__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
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pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
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@ -362,11 +371,24 @@ static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
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phylink_set(mask, 1000baseT_Half);
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}
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/* On the RTL9300 family of SoCs, ports 26 to 27 may be SFP ports TODO: take out of .dts */
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if (port >= 26 && port <= 27)
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// Internal phys of the RTL93xx family provide 10G
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if (priv->ports[port].phy_is_integrated
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&& state->interface == PHY_INTERFACE_MODE_1000BASEX) {
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phylink_set(mask, 1000baseX_Full);
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} else if (priv->ports[port].phy_is_integrated) {
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phylink_set(mask, 1000baseX_Full);
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if (port >= 26 && port <= 27)
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phylink_set(mask, 10000baseKR_Full);
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phylink_set(mask, 10000baseSR_Full);
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phylink_set(mask, 10000baseCR_Full);
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}
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if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
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phylink_set(mask, 1000baseX_Full);
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phylink_set(mask, 1000baseT_Full);
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phylink_set(mask, 10000baseKR_Full);
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phylink_set(mask, 10000baseT_Full);
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phylink_set(mask, 10000baseSR_Full);
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phylink_set(mask, 10000baseCR_Full);
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}
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phylink_set(mask, 10baseT_Half);
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phylink_set(mask, 10baseT_Full);
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@ -377,6 +399,7 @@ static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
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__ETHTOOL_LINK_MODE_MASK_NBITS);
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bitmap_and(state->advertising, state->advertising, mask,
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__ETHTOOL_LINK_MODE_MASK_NBITS);
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pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
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}
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static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
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@ -482,6 +505,13 @@ static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
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pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
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}
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if (priv->family_id == RTL9310_FAMILY_ID
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&& (port >= 52 || port <= 55)) { /* Internal serdes */
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state->speed = SPEED_10000;
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state->link = 1;
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state->duplex = 1;
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}
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pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
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state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
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if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
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@ -559,7 +589,7 @@ static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
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if (priv->family_id == RTL8380_FAMILY_ID) {
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if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
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pr_debug("PHY autonegotiates\n");
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reg |= BIT(2);
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reg |= RTL838X_NWAY_EN;
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sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
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rtl83xx_config_interface(port, state->interface);
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return;
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@ -569,19 +599,25 @@ static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
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if (mode != MLO_AN_FIXED)
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pr_debug("Fixed state.\n");
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/* Clear id_mode_dis bit, and the existing port mode, let
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* RGMII_MODE_EN bet set by mac_link_{up,down} */
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if (priv->family_id == RTL8380_FAMILY_ID) {
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/* Clear id_mode_dis bit, and the existing port mode, let
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* RGMII_MODE_EN bet set by mac_link_{up,down}
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*/
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reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
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reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
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if (state->pause & MLO_PAUSE_TXRX_MASK) {
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if (state->pause & MLO_PAUSE_TX)
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reg |= TX_PAUSE_EN;
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reg |= RX_PAUSE_EN;
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reg |= RTL838X_TX_PAUSE_EN;
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reg |= RTL838X_RX_PAUSE_EN;
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}
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} else if (priv->family_id == RTL8390_FAMILY_ID) {
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reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
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if (state->pause & MLO_PAUSE_TXRX_MASK) {
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if (state->pause & MLO_PAUSE_TX)
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reg |= RTL839X_TX_PAUSE_EN;
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reg |= RTL839X_RX_PAUSE_EN;
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}
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}
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reg &= ~(3 << speed_bit);
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switch (state->speed) {
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case SPEED_1000:
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@ -590,22 +626,98 @@ static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
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case SPEED_100:
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reg |= 1 << speed_bit;
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break;
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default:
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break; // Ignore, including 10MBit which has a speed value of 0
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}
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if (priv->family_id == RTL8380_FAMILY_ID) {
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reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
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reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
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if (state->link)
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reg |= FORCE_LINK_EN;
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if (state->duplex == DUPLEX_FULL)
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reg |= DUPLX_MODE;
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reg |= RTL838X_FORCE_LINK_EN;
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if (state->duplex == RTL838X_DUPLEX_MODE)
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reg |= RTL838X_DUPLEX_MODE;
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} else if (priv->family_id == RTL8390_FAMILY_ID) {
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reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
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if (state->link)
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reg |= RTL839X_FORCE_LINK_EN;
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if (state->duplex == RTL839X_DUPLEX_MODE)
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reg |= RTL839X_DUPLEX_MODE;
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}
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// Disable AN
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if (priv->family_id == RTL8380_FAMILY_ID)
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reg &= ~BIT(2);
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reg &= ~RTL838X_NWAY_EN;
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sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
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}
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static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
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unsigned int mode,
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const struct phylink_link_state *state)
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{
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struct rtl838x_switch_priv *priv = ds->priv;
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int sds_num;
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u32 reg, band;
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sds_num = priv->ports[port].sds_num;
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pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
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switch (state->interface) {
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case PHY_INTERFACE_MODE_HSGMII:
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pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
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band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
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rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
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band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
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break;
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case PHY_INTERFACE_MODE_1000BASEX:
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band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
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rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
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break;
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case PHY_INTERFACE_MODE_XGMII:
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band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
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rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
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break;
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case PHY_INTERFACE_MODE_10GBASER:
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case PHY_INTERFACE_MODE_10GKR:
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band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
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rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
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break;
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case PHY_INTERFACE_MODE_USXGMII:
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// Translates to MII_USXGMII_10GSXGMII
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band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
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rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
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band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
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rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
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band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
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break;
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case PHY_INTERFACE_MODE_QSGMII:
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band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
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rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
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break;
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default:
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pr_err("%s: unknown serdes mode: %s\n",
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__func__, phy_modes(state->interface));
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return;
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}
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reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
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pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
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reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
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reg &= ~(0xf << 12);
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reg |= 0x2 << 12; // Set SMI speed to 0x2
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reg |= BIT(17) | BIT(16); // Enable RX pause and TX pause
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if (state->duplex == DUPLEX_FULL)
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reg |= RTL931X_DUPLEX_MODE;
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sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
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}
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static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
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unsigned int mode,
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const struct phylink_link_state *state)
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@ -621,6 +733,9 @@ static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
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if (port == priv->cpu_port)
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return;
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if (priv->family_id == RTL9310_FAMILY_ID)
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return rtl931x_phylink_mac_config(ds, port, mode, state);
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reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
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reg &= ~(0xf << 3);
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@ -672,12 +787,16 @@ static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
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}
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if (state->link)
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reg |= FORCE_LINK_EN;
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reg |= RTL930X_FORCE_LINK_EN;
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if (state->duplex == DUPLEX_FULL)
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reg |= BIT(2);
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reg |= RTL930X_DUPLEX_MODE;
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if (priv->ports[port].phy_is_integrated)
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reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
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else
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reg |= RTL930X_FORCE_EN;
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reg |= 1; // Force Link up
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sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
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}
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@ -1799,7 +1918,7 @@ const struct dsa_switch_ops rtl83xx_switch_ops = {
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const struct dsa_switch_ops rtl930x_switch_ops = {
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.get_tag_protocol = rtl83xx_get_tag_protocol,
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.setup = rtl930x_setup,
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.setup = rtl93xx_setup,
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.phy_read = dsa_phy_read,
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.phy_write = dsa_phy_write,
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@ -147,12 +147,34 @@
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#define RTL930X_MAC_LINK_MEDIA_STS (0xCB14)
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/* MAC link state bits */
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#define FORCE_EN (1 << 0)
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#define FORCE_LINK_EN (1 << 1)
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#define NWAY_EN (1 << 2)
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#define DUPLX_MODE (1 << 3)
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#define TX_PAUSE_EN (1 << 6)
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#define RX_PAUSE_EN (1 << 7)
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#define RTL838X_FORCE_EN (1 << 0)
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#define RTL838X_FORCE_LINK_EN (1 << 1)
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#define RTL838X_NWAY_EN (1 << 2)
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#define RTL838X_DUPLEX_MODE (1 << 3)
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#define RTL838X_TX_PAUSE_EN (1 << 6)
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#define RTL838X_RX_PAUSE_EN (1 << 7)
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#define RTL838X_MAC_FORCE_FC_EN (1 << 8)
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#define RTL839X_FORCE_EN (1 << 0)
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#define RTL839X_FORCE_LINK_EN (1 << 1)
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#define RTL839X_DUPLEX_MODE (1 << 2)
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#define RTL839X_TX_PAUSE_EN (1 << 5)
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#define RTL839X_RX_PAUSE_EN (1 << 6)
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#define RTL839X_MAC_FORCE_FC_EN (1 << 7)
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#define RTL930X_FORCE_EN (1 << 0)
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#define RTL930X_FORCE_LINK_EN (1 << 1)
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#define RTL930X_DUPLEX_MODE (1 << 2)
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#define RTL930X_TX_PAUSE_EN (1 << 7)
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#define RTL930X_RX_PAUSE_EN (1 << 8)
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#define RTL930X_MAC_FORCE_FC_EN (1 << 9)
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#define RTL931X_FORCE_EN (1 << 9)
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#define RTL931X_FORCE_LINK_EN (1 << 0)
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#define RTL931X_DUPLEX_MODE (1 << 2)
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#define RTL931X_MAC_FORCE_FC_EN (1 << 4)
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#define RTL931X_TX_PAUSE_EN (1 << 16)
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#define RTL931X_RX_PAUSE_EN (1 << 17)
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/* EEE */
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#define RTL838X_MAC_EEE_ABLTY (0xa1a8)
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@ -433,6 +455,7 @@ enum phy_type {
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PHY_RTL8218B_EXT = 3,
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PHY_RTL8214FC = 4,
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PHY_RTL839X_SDS = 5,
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PHY_RTL930X_SDS = 6,
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};
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struct rtl838x_port {
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@ -441,6 +464,7 @@ struct rtl838x_port {
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u16 pvid;
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bool eee_enabled;
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enum phy_type phy;
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bool phy_is_integrated;
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bool is10G;
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bool is2G5;
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int sds_num;
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@ -453,7 +477,12 @@ struct rtl838x_vlan_info {
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u8 profile_id;
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bool hash_mc_fid;
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bool hash_uc_fid;
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u8 fid;
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u8 fid; // AKA MSTI
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// The following fields are used only by the RTL931X
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int if_id; // Interface (index in L3_EGR_INTF_IDX)
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u16 multicast_grp_mask;
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int l2_tunnel_list_id;
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};
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enum l2_entry_type {
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@ -488,6 +517,15 @@ struct rtl838x_l2_entry {
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u16 mc_mac_index;
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u16 nh_route_id;
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bool nh_vlan_target; // Only RTL83xx: VLAN used for next hop
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// The following is only valid on RTL931x
|
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bool is_open_flow;
|
||||
bool is_pe_forward;
|
||||
bool is_local_forward;
|
||||
bool is_remote_forward;
|
||||
bool is_l2_tunnel;
|
||||
int l2_tunnel_id;
|
||||
int l2_tunnel_list_id;
|
||||
};
|
||||
|
||||
enum fwd_rule_action {
|
||||
@ -500,6 +538,17 @@ enum pie_phase {
|
||||
PHASE_IACL = 1,
|
||||
};
|
||||
|
||||
enum igr_filter {
|
||||
IGR_FORWARD = 0,
|
||||
IGR_DROP = 1,
|
||||
IGR_TRAP = 2,
|
||||
};
|
||||
|
||||
enum egr_filter {
|
||||
EGR_DISABLE = 0,
|
||||
EGR_ENABLE = 1,
|
||||
};
|
||||
|
||||
/* Intermediate representation of a Packet Inspection Engine Rule
|
||||
* as suggested by the Kernel's tc flower offload subsystem
|
||||
* Field meaning is universal across SoC families, but data content is specific
|
||||
|
||||
@ -125,6 +125,9 @@ void rtl930x_print_matrix(void);
|
||||
|
||||
/* RTL931x-specific */
|
||||
irqreturn_t rtl931x_switch_irq(int irq, void *dev_id);
|
||||
int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode);
|
||||
int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode);
|
||||
void rtl931x_sds_init(u32 sds, phy_interface_t mode);
|
||||
|
||||
#endif /* _NET_DSA_RTL83XX_H */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user