Commit Graph

529 Commits

Author SHA1 Message Date
Olliver Schinagl
9cec4a0ea4
realtek: Use built-in functionality for timeout loop
In commit 81e3017609 ("realtek: clean up rtl838x MDIO busy wait loop")
a hand-crafted loop was created, that nearly exactly replicate the
iopoll's `read_poll_timeout` functionality.

Use that instead.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2022-09-14 12:03:57 +02:00
Alexandru Gagniuc
01e2184c49 realtek: add support for TP-Link SG2210P
Add support for the TP-Link SG2210P switch. This is an RTL8380 based
switch with eight RJ-45 ports with 802.3af PoE, and two SFP ports.

This device shares the same board with the SG2008P and SG2008. To
model this, declare all the capabilities in the sg2xxx dtsi, and
disable unpopulated on the lower end models.

Specifications:
---------------
 - SoC:       Realtek RTL8380M
 - Flash:     32 MiB SPI flash (Vendor varies)
 - RAM:	      256 MiB (Vendor varies)
 - Ethernet:  8x 10/100/1000 Mbps with PoE (all ports)
              2x SFP ports
 - Buttons:   1x "Reset" button on front panel
 - Power:     53.5V DC barrel jack
 - UART:      1x serial header, unpopulated
 - PoE:       2x TI TPS23861 I2C PoE controller

Works:
------
  - (8) RJ-45 ethernet ports
  - (2) SFP ports (with caveats)
  - Switch functions
  - System LED

Not yet enabled:
----------------
  - Power-over-Ethernet (driver works, but doesn't enable "auto" mode)
  - PoE LEDs

Enabling SFP ports:
-------------------

The SFP port control lines are hardwired, except for tx-disable. These
lines are controller by the RTL8231 in shift register mode. There is
no driver support for this yet.

However, to enable the lasers on SFP1 and SFP2 respectively:

    echo 0x0510ff00 > /sys/kernel/debug/rtl838x/led/led_p_en_ctrl
    echo      0x140 > /sys/kernel/debug/rtl838x/led/led_sw_p_ctrl.26
    echo      0x140 > /sys/kernel/debug/rtl838x/led/led_sw_p_ctrl.24

Install via serial console/tftp:
--------------------------------

The footprints R27 (0201) and R28 (0402) are not populated. To enable
serial console, 50 ohm resistors should be soldered -- any value from
0 ohm to 50 ohm will work. R27 can be replaced by a solder bridge.

The u-boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.

Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. The sysupgrade image can also be flashed. To install OpenWrt:

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"

Power on device, and stop boot by pressing any key.
Once the shell is active:
 1. Ground out the CLK (pin 16) of the ROM (U7)
 2. Select option "3. Start"
 3. Bootloader notes that "The kernel has been damaged!"
 4. Release CLK as sson as bootloader thinks image is corrupted.
 5. Bootloader enters automatic recovery -- details printed on console
 6. Watch as the bootloader flashes and boots OpenWrt.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[OpenWrt capitalisation in commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-13 09:22:26 +02:00
Alexandru Gagniuc
ab2a4c1e01 realtek: rtl8380-tl-sg2xxx: use a single "firmware" partition
The "firmware" partition was assembled from two contiguous partitions.
This complexity is unnecessary. Instead of using mtd-concat over
"sys" and "usrimg1", simply declare the "firmware" partition to cover
the flash space instead.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-09-13 09:22:26 +02:00
Alexandru Gagniuc
d55c087390 realtek: tl-sg2xxx: read MAC address from nvmem-cells
The TP-Link RTL83xx based switches have their MAC address programmed
in the "para" partition. While in theory, the format of this partition
is dynamic, in practice, the MAC address appears to be located at a
consistent address. Thus, use nvmem-cells to read this MAC address.

The main MAC is required for deriving the MAC address of the switch
ports. Instead of reading it via mtd_get_mac_binary(), alias the
ethernet0 node as the label-mac-device, and use get_mac_label().

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-09-13 09:22:26 +02:00
Alexandru Gagniuc
5f026f1272 realtek: rtl838x: label switch port dts nodes
Although PHY nodes are labeled, the port nodes were not. Labeling of
ports is useful for 'status = "disabled"' ports, which is supported
since commit 9a7f17e11f ("realtek: ignore disabled switch ports")

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-09-13 09:22:26 +02:00
Alexandru Gagniuc
bc9dcfb1ce realtek: split TP-Link SG2000 series devicetree
The TP-Link TL-SG2008, TL-SG2008P, and TL-SG2210P use the same board.
The main difference is that some footprints are not populated in the
lower-end models. To model this with minimal duplication, move the
devicetree to a common dtsi, leaving out just the board name.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[remove port relabelling from commit message, already merged with commit
 18a2b29aa1 ("realtek: tl-sg2008p: fix labeling of lan ports")]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-13 09:22:26 +02:00
Andreas Böhler
5f8c86e654 realtek: add support for TP-Link SG2452P v4 aka T1600G-52PS v4
This is an RTL8393-based switch with 802.3af on all 48 ports.

Specifications:
---------------
 * SoC:       Realtek RTL8393M
 * Flash:     32 MiB SPI flash
 * RAM:       256 MiB
 * Ethernet:  48x 10/100/1000 Mbps with PoE+
 * Buttons:   1x "Reset" button, 1x "Speed" button
 * UART:      1x serial header, unpopulated
 * PoE:       12x TI TPS23861 I2C PoE controller, 384W PoE budget
 * SFP:       4 SFP ports

Works:
------
  - (48) RJ-45 ethernet ports
  - Switch functions
  - Buttons
  - All LEDs on front panel except port LEDs
  - Fan monitoring and basic control

Not yet enabled:
----------------
  - PoE - ICs are not in AUTO mode, so the kernel driver is not usable
  - Port LEDs
  - SFP cages

Install via web interface:
-------------------------

Not supported at this time.

Install via serial console/tftp:
--------------------------------

The U-Boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.

Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. To install OpenWRT:

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"

Power on device, and stop boot by pressing any key.
Once the shell is active:
 1. Ground out the CLK (pin 16) of the ROM (U6)
 2. Select option "3. Start"
 3. Bootloader notes that "The kernel has been damaged!"
 4. Release CLK as soon as bootloader thinks image is corrupted.
 5. Bootloader enters automatic recovery -- details printed on console
 6. Watch as the bootloader flashes and boots OpenWRT.

Blind install via tftp:
-----------------------

This method works when it's not feasible to install a serial header.

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"
 3. Watch network traffic (tcpdump or wireshark works)
 4. Power on the device.
 5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U6)
 6. When 192.168.0.30 makes tftp requests, release pin 16
 7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT

Signed-off-by: Andreas Böhler <dev@aboehler.at>
2022-09-10 22:13:52 +02:00
Bjørn Mork
2ca5602864 realtek: fix RTL839x receive tag decoding
The previous fixup was incomplete, and the offsets for the
queue and crc_error cpu_tag bitfields were still wrong on
RTL839x.

Fixes: 545c6113c9 ("realtek: fix RTL838x receive tag decoding")
Suggested-by: Jan Hoffmann <jan@3e8.eu>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
2022-09-09 22:11:55 +02:00
Bjørn Mork
545c6113c9 realtek: fix RTL838x receive tag decoding
Commit dc9cc0d3e2 ("realtek: add QoS and rate control") replaced a
16 bit reserved field in the RTL83xx packet header with the initial
cpu_tag word, shifting the real cpu_tag fields by one.  Adjusting for
this new shift was partially forgotten in the new RX tag decoders.

This caused the switch to block IGMP, effectively blocking IPv4
multicast.

The bug was partially fixed by commit 9d847244d9 ("realtek: fix
RTL839X receive tag decoding")

Fix on RTL838x too, including correct NIC_RX_REASON_SPECIAL_TRAP value.

Suggested-by: Jan Hoffmann <jan@3e8.eu>
Fixes: dc9cc0d3e2 ("realtek: add QoS and rate control")
Signed-off-by: Bjørn Mork <bjorn@mork.no>
2022-09-08 22:28:15 +02:00
Sander Vanheule
f1802b0db7 realtek: replace fix for spurious GPIO interrupts
8 and 16 bit writes to the GPIO peripheral are apparently not supported,
and only worked most of the time. This resulted in garbabe writes to the
interrupt mask registers, causing spurious unhandled interrupts, which
could lead to CPU lock-ups as these kept retriggering.

Instead of clearing these spurious interrupt when they occur, the
upstream patch will just make sure all register writes have the intended
result, so these don't happen at all.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-04 20:55:15 +02:00
Markus Stockhausen
78c0fb6927 realtek: Fix missing clock module CONFIG setting
Since introduction of clock driver we have a new kernel config
setting. Provide an initial value for the 930x targets.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-31 23:25:39 +02:00
Markus Stockhausen
6ff21c436d realtek: fix PLL register inconsistencies
Some devices have wrong/empty values in the PLL registers. Work
around that by reporting the default values.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-31 23:25:39 +02:00
John Audia
e0753c5d5c kernel: bump 5.10 to 5.10.139
All patches automatically rebased.

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-08-31 23:25:39 +02:00
Alexandru Gagniuc
18a2b29aa1 realtek: tl-sg2008p: fix labeling of lan ports
The SG2008P has its ethernet ports in the rear, and LEDs in the front.
The ports should be labeled lan8->lan1, not lan1->lan8. To resolve
this, fix the phy mapping in the "ports" node.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-08-29 11:54:00 +02:00
Alexandru Gagniuc
f242f642bb realtek: tl-sg2008p: use correct i2c address for TPS23861
Address 0x30 is a "broadcast" address for the TPS23861. It should not
be used by drivers, as all TPS23861 devices on the bus are supposed to
respond. Change this to the correct address, 0x28.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-08-29 11:54:00 +02:00
Sander Vanheule
9a7f17e11f realtek: ignore disabled switch ports
When marking a switch port as disabled in the device tree, by using
'status = "disabled";', the switch driver fails on boot, causing a
restart:

    CPU 0 Unable to handle kernel paging request at virtual address
    00000000, epc == 802c3064, ra == 8022b4b4
        [ ... ]
    Call Trace:
    [<802c3064>] strlen+0x0/0x2c
    [<8022b4b4>] start_creating.part.0+0x78/0x194
    [<8022bd3c>] debugfs_create_dir+0x44/0x1c0
    [<80396dfc>] rtl838x_dbgfs_port_init+0x54/0x258
    [<80397508>] rtl838x_dbgfs_init+0xe0/0x56c

This is caused by the DSA subsystem (mostly) ignoring the port, while
rtl83xx_mdio_probe() still extracts some details on this disabled port
from the device tree, resulting in the usage of a NULL pointer where a
port name is expected.

By not probing ignoring disabled ports, no attempt is made to create a
debugfs directory later. The device then boots as expected without the
disabled port.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-29 08:32:42 +02:00
Markus Stockhausen
48f3746fe5 realtek: switch RTL838X/RTL839X DT to new clock driver
Use new DT clockdriver syntax for RTL838X/RTL839X targets. To make it work
we need to change some nodes:
- define the external oscillator speed (25MHz)
- define SRAM
- add clock controller
- Add second CPU for RTL839X
- map all devices to new clocks
- Remove dummy LXB clock
- add CPU OPP table

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-28 11:48:30 +02:00
Markus Stockhausen
7c18aab6e0 realtek: activate clock driver for RTL838X/RTL839X targets
Make use the new clock driver for RTL838X and RTL839x target devices. Of course
we will enable their primary consumer (cpufreq-dt) too. To be careful just set
the default governor to userspace. As we rely on SRAM activate that module too.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-28 11:48:30 +02:00
Markus Stockhausen
5df36d4849 realtek: enable basic config for cpufreq framework
A new clock driver makes more sense if it can be used from consumers
like cpufreq.  Before we enable the driver we must tell the config that
the RTL838X and RTL839X targets allow CPU frequency changing.

Even though these targets currently rely on the CPU's internal R4K
timer, MIPS_EXTERNAL_TIMER is selected to allow for CPU frequency change
testing. The Realtek timers, which are clocked by the Lexra bus, still
need to be supported and used in order to provide correct wall times
when reclocking the CPU.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[add paragraph about MIPS_EXTERNAL_TIMER to commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-28 11:45:03 +02:00
Markus Stockhausen
800d5fb3c6 realtek: add patch to enable new clock driver in kernel
Allow building the clock driver with kernel config options.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-28 11:31:21 +02:00
Markus Stockhausen
4850bd887c realtek: add RTL83XX clock driver
Add a new self-contained combined clock & platform driver that allows to
access the PLL hardware clocks of RTL83XX devices. Currently it provides
info about CPU, MEM and LXB clocks on RTL838X and RTL839X devices and
additionally allows to change the CPU clocks. Changing the clocks
multiple times on a DGS-1210-20 and a DGS-1210-52 already works well and
is multithreading safe on the RTL839X. Even a cpufreq initiated change
of the CPU clock works fine. Loading the driver will add some meaningful
logging.

[0.000000] rtl83xx-clk: initialized, CPU 500 MHz, MEM 300 MHz (8 Bit DDR3), LXB 200 MHz
[0.279456] rtl83xx-clk soc:clock-controller: rate setting enabled, CPU 325-600 MHz,
           MEM 300-300 MHz, LXB 200-200 MHz, OVERCLOCK AT OWN RISK

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[remove trailing whitespaces, C-style SPDX comments for ASM and headers]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-28 11:30:58 +02:00
Markus Stockhausen
1efaad03bb realtek: add PLL DT binding includes
Add some constants for sharing between DT and drivers.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-28 11:03:34 +02:00
Markus Stockhausen
396e190f0b realtek: more generic platform initialization
Platform startup still "guesses" the CPU clock speed by DT fixed values.
If possible take clock rates from a to be developed driver and align to
MIPS generic platfom initialization code. Pack old behaviour into a
fallback function. We might get rid of that some day.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-20 11:49:30 +02:00
Daniel Groth
8c04a5c456 realtek: d-link: add support for dgs-1210-10mp
General hardware info:
-------------------------------------------------------------------------------

D-Link DGS-1210-10MP is a switch with 8 ethernet ports and 2 SFP ports, all
ports Gbit capable. It is based on a RTL8380 SoC @ 500MHz, DRAM 128MB and
32MB flash. All ethernet ports are 802.3af/at PoE capable
with a total PoE power budget of 130W.

File info:
-------------------------------------------------------------------------------
The dgs-1210-10mp is very similar to dgs-1210-10p so I used that as a start.

rtl838x.mk:
 - Removed lua-rs232 package since it was a leftover from the old rtl83xx-poe
   package.
 - Updated the soc to 8380.
 - Specified device variant: F.
 - Installed the new realtek-poe package.

rtl8380_d-link_dgs-1210-10mp.dts:
 - Moved dgs-1210 family common parts and non PoE related ports on rtl8231
   to the new device tree dtsi files.

Serial connection:
-------------------------------------------------------------------------------
The UART for the SoC (115200 8N1) is available close to the front panel next
to the LED/key card connector via unpopulated standard 0.1" pin header
marked j4. Pin1 is marked with arrow and square.

Pin 1: Vcc 3,3V
Pin 2: Tx
Pin 3: Rx
Pin 4: Gnd

Installation with TFTP from u-boot
-------------------------------------------------------------------------------
I originally used the install procedure:
'OpenWrt installation using the TFTP method and serial console access' found
in the device wiki for the dgs-1210-16.
< https://openwrt.org/toh/d-link/dgs-1210-16_g1#openwrt_installation_using
_the_tftp_method_and_serial_console_access >

About the realtek-poe package
-------------------------------------------------------------------------------
The realtek-poe package is installed but there isn't any automatic PoE config
setting at this time so for now the PoE config must be edited manually.

Original OEM hardware/firmware data at first installation
-------------------------------------------------------------------------------
It has been installed, developed, and tested on a device with these OEM
hardware and firmware versions.

- U-boot: 2011.12.(2.1.5.67086)-Candidate1 (Jun 22 2020 - 15:03:58)
- Boot version: 1.01.001
- Firmware version: 6.20.007
- Hardware version: F1

Things to be done when support are developed
-------------------------------------------------------------------------------
 - realtek-poe has been included in OpenWrt but the automatic config handling
   has not been solved yet so in the future there will probably be some minor
   updates for this device to handle the poe config.
 - LED link_act and poe are per function supposed to be connected to the PoE
   system.
   But some software development is also needed to make this LED work and
   shift the LED array between act and poe indication and to shift the mode
   lights with mode key.
 - LED poe_max should probably be used as straight forward error output from
   the realtek-poe package error handling. But no code has been written for
   this.
 - SFP is currently not hot pluggable. Development is under progress to get
   working I2C communication with SFP and have them hot pluggable.
   When any device in the dgs-1210 family gets this working, I expect it
   should be possible to implement the same solution in this device.

Signed-off-by: Daniel Groth <flygarn12@gmail.com>
[Capitalisation of abbreviations, DEVICE_VARIANT and update filenames,
device compatibles on single line]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-20 09:02:44 +02:00
Daniel Groth
51ec9b3864 realtek: d-link: dgs-1210 remake of the device tree
I have collected the known information from the dts files we have.
After that I made a new device tree that should work for this whole D-Link
switch family.
This device tree is based on modules where you first select which SoC group
the device belongs to. Then you include the GPIO dtsi file depending on what
hardware your device has, see examples below.
This tree is also expandable for more hardware,
see the part 'Future expansion possibilities' further down.

-------------------------------------------------------------------------------
The device tree now looks like this:
                            ----------------
                            | rtl838x.dtsi |    // Note 1.
                            ----------------
                                    |
                                    |
                    ---------------------------------------
                    | rtl838x_d-link_dgs-1210_common.dtsi | // Note 2.
                    ---------------------------------------
                                |
                                |       --------------
                                |-------| device.dts |      // Note 3.
                                |       --------------
                                |
                -------------------------------------
                | rtl83xx_d-link_dgs-1210_gpio.dtsi |       // Note 4.
                -------------------------------------
                                |
                                |       --------------
                                |-------| device.dts |      // Note 5.
                                        --------------

Note 1; Included in rtl838x_d-link_dgs-1210_common.dtsi.

Note 2; SoC level information and memory mapping. Choose which one to include
		in the device dts.

Note 3; At this point dgs-1210-16 will come out here.

Note 4; In this dtsi only common board hardware based on the rtl8231 is found.
	No PoE based hardware in this dtsi.
	In this dtsi there is no <#include> to above *_common.dtsi.

Note 5; Device dts with only rtl8231 based hardware without PoE will come out
		here.

-------------------------------------------------------------------------------
How to set up in dts file:

The device dts will have one of these two <#include> alternatives.

This alternative includes only common features:
<#include "rtl838x_d-link_dgs-1210_common.dtsi">

This alternative includes common and the rtl8231 GPIO (no PoE) features:

<#include "rtl838x_d-link_dgs-1210_common.dtsi">
<#include "rtl83xx_d-link_dgs-1210_gpio.dtsi">

-------------------------------------------------------------------------------
Implementation:

Finally, I also implemented this new family device tree on the current
supported devices:
dgs-1210-10p
dgs-1210-16
dgs-1210-20
dgs-1210-28

The implementation for the dgs-1210-10p is different. I have removed the
information from the rtl8382_d-link_dgs-1210-10p.dts that is already present
in rtl838x_d-link_dgs-1210_common.dtsi.
Since the rest isn't officially probed in the device dts I do not want to
include the rtl83xx_d-link_dgs-1210_gpio.dtsi with dgs-1210-10p.dts.

Since I don't have these devices to test on I have built the original firmware
for each one of these devices before this change and saved the dtb file and
then compared the original dtb file with the dtb file built with this new
device tree.

-------------------------------------------------------------------------------
Future expansion possibilities:

In parallel with the rtl838x_d-link_dgs-1210_common.dtsi in the tree map
we can make a rtl839x_d-link_dgs-1210_common.dtsi to use the rtl839x.dtsi if
the need arises with more devices based on rtl839x soc.

When we have more PoE devices so the hardware map for these gets more clear
we can make a rtl83xx_d-link_dgs-1210_poe.dtsi below
the rtl83xx_d-link_dgs-1210_gpio.dtsi in the tree map.

I looked at the port and switch setup to see if it could be moved to the dtsi.
I decided not to touch this part now. The reason was that there isn't really
any meaningful way this could be shared between the devices.
The only thing in common over the family is the 8+2sfp ports on the
dgs-1210-10xx device.
And then there is the hot plug SFP and I2C ports that aren’t implemented
on any device. So maybe when we see the whole port map for the family
then maybe the ports can be moved to a *_common.dtsi but I don't think it is
the right moment for that now.

Signed-off-by: Daniel Groth <flygarn12@gmail.com>
[Capitalisation of abbreviations and 'D-Link']
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-20 09:02:44 +02:00
Alexandru Gagniuc
6d5873a162 realtek: add support for TP-Link SG2008P
Add support for the TP-Link SG2008P switch. This is an RTL8380 based
switch with 802.3af one the first four ports.

Specifications:
---------------
 * SoC:       Realtek RTL8380M
 * Flash:     32 MiB SPI flash (Vendor varies)
 * RAM:       256 MiB (Vendor varies)
 * Ethernet:  8x 10/100/1000 Mbps with PoE on 4 ports
 * Buttons:   1x "Reset" button on front panel
 * Power:     53.5V DC barrel jack
 * UART:      1x serial header, unpopulated
 * PoE:       1x TI TPS23861 I2C PoE controller

Works:
------
  - (8) RJ-45 ethernet ports
  - Switch functions
  - System LED

Not yet enabled:
----------------
  - Power-over-Ethernet (driver works, but doesn't enable "auto" mode)
  - PoE, Link/Act, PoE max and System LEDs

Install via web interface:
-------------------------

Not supported at this time.

Install via serial console/tftp:
--------------------------------

The footprints R27 (0201) and R28 (0402) are not populated. To enable
serial console, 50 ohm resistors should be soldered -- any value from
0 ohm to 50 ohm will work. R27 can be replaced by a solder bridge.

The u-boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.

Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. The sysupgrade image can also be flashed. To install OpenWRT:

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"

Power on device, and stop boot by pressing any key.
Once the shell is active:
 1. Ground out the CLK (pin 16) of the ROM (U7)
 2. Select option "3. Start"
 3. Bootloader notes that "The kernel has been damaged!"
 4. Release CLK as sson as bootloader thinks image is corrupted.
 5. Bootloader enters automatic recovery -- details printed on console
 6. Watch as the bootloader flashes and boots OpenWRT.

Blind install via tftp:
-----------------------

This method works when it's not feasible to install a serial header.

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"
 3. Watch network traffic (tcpdump or wireshark works)
 4. Power on the device.
 5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U7)
 6. When 192.168.0.30 makes tftp requests, release pin 16
 7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-08-13 19:59:47 +02:00
Alexandru Gagniuc
7bba7ccde9 realtek: EnGenius EWS2910P: use the mtd3 partition for root overlay
The root overlay is mounted on the "rootfs_data" partition. This comes
at the end of the firmware image, courtesy of mtdsplit. There is very
little space left (About 1MB), which can fill up rapidly.

The "firmware" and "firmware2" partitions are part of the bootloader
dual firmware logic. They should contain independent, valid uImages.
This leaves "jffs2-cfg" (mtd3) and "jffs2-log" (mtd4) as candidates.

mtd3 is about 13.7 MB and is used by the vendor firmware to store
configuration settings. It is only erased by vendor firmware during a
factory reset. By naming this partition "rootfs_data", it becomes the
root overlay, providing significantly more room. Even with mtdsplit
wanting to create a "rootfs_data" on the firmware partition, mtd3 is
used as the overlay.

Rename "jffs2-cfg" to "rootfs_data", and profit from the extra space.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-08-13 19:19:38 +02:00
Sander Vanheule
225137608c realtek: Netgear GS110TPP v1: add lan9 and lan10
The original commit for the GS110TP was missing ports 9 and 10. These
are provided by an external RTL8214C phy, for which no support was
available at the time. Now that this phy is supported, add the missing
entries to enable all device ports.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-13 19:15:46 +02:00
Paul Spooren
ead7e5b4c3 realtek: skip SFP ports in PoE setup
The function `ucidef_set_poe` receives a list of ports to add to the PoE array.
Since switches have many ports the varibale `lan_list` is passed instead of
writing every single lan port. However, this list includes partly SFP ports
which are unrelated to PoE.

This commits adds the option to add a third parameter to manually exclide
interfaces, usually the last two.

Signed-off-by: Paul Spooren <mail@aparcar.org>
[Replace glob by regex to be more specific about matching characters]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-13 19:15:46 +02:00
Hauke Mehrtens
ff06edd1f0 kernel: Activate CONFIG_GPIOLIB in generic configuration
All targets expect the malta target already activate the CONFIG_GPIOLIB
option. Move it to generic kernel configuration and also activate it for
malta.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2022-08-10 21:36:17 +02:00
INAGAKI Hiroshi
cef3f05a55 realtek: add support for Panasonic Switch-M48eG PN28480K
Panasonic Switch-M48eG PN28480K is a 48 + 4 port gigabit switch, based on
RTL8393M.

Specification:

- SoC           : Realtek RTL8393M
- RAM           : DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash         : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet      : 10/100/1000 Mbps x48 + 2
  - port  1-40  : TP, RTL8218B x5
  - port 41-48  : RTL8218FB
    - port 41-44: TP
    - port 45-48: TP/SFP (Combo)
- LEDs/Keys     : 7x / 1x
- UART          : RS-232 port on the front panel (connector: RJ-45)
  - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
  - 9600n8
- Power         : 100-240 VAC, 50/60 Hz, 0.5 A
  - Plug        : IEC 60320-C13
- Stock OS      : VxWorks based

Flash instruction using initramfs image:

1.  Prepare the TFTP server with the IP address 192.168.1.111
2.  Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
    the TFTP directory
3.  Download the official upgrading firmware (ex: pn28480k_v30000.rom)
    and place it to the TFTP directory
4.  Boot M48eG and interrupt the U-Boot with Ctrl + C keys
5.  Execute the following commands and boot with the OpenWrt initramfs
    image

    rtk network on
    tftpboot 0x81000000
    bootm

6.  Backup mtdblock files to the computer by scp or anything and reboot
7.  Interrupt the U-Boot and execute the following commands to re-create
    filesystem in the flash

    ffsmount c:/
    ffsfmt c:/

    this step takes a long time, about ~ 4 mins

8.  Execute the following commands to put the official images to the
    filesystem

    updatert <official image>

    example:

      updatert pn28480k_v30000.rom

    this step takes about ~ 40 secs

9.  Set the environment variables of the U-Boot by the following commands

    setenv loadaddr 0xb4e00000
    setenv bootcmd 'sleep 10; bootm;'
    saveenv

    'sleep 10;' is required as dummy to execute 'bootm' command correctly

10: Download the OpenWrt initramfs image and boot with it

    tftpboot 0x81000000 0101A8C0.img
    bootm

11: On the initramfs image, download the sysupgrade image and perform
    sysupgrade with it

    sysupgrade <imagename>

12: Wait ~ 120 seconds to complete flashing

Known Issues:

- 4x SFP ports are provided as combo ports by the RTL8218FB chip, but the
  phy driver has no support for it. Currently, only TP ports work by the
  RTL8218B support.

Note:

- "Switch-M48eG" is a model name, and "PN28480K" is a model number.
  Switch-M48eG has an another (old) model number ("PN28480"), it's not a
  Realtek based hardware.

- Switch-M48eG has a "POWER" LED (Green), but it's not connected to any
  GPIO pin.

- U-Boot checks the runtime images in the flash when booting and fails
  to execute "bootcmd" variable if the images are not existing.

- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
  firmware and it includes the stock images, configuration files and
  checksum files. It's unknown format, can't be managed on the OpenWrt.
  To get the enough space for OpenWrt, move the filesystem to the head
  of "fs_reserved" partition by execution of "ffsfmt" and "updatert".

- A GPIO pin on PCA9539 is used for resetting external RTL8218B phys and
  RTL8218FB phy.
  This should be specified as "reset-gpios" property in MDIO node, but
  the current configuration of RTL8218B phy in the driver seems to be
  incomplete and RTL8218FB won't be configured on RTL8218D support.
  So, ethernet ports on these phys will be broken after hard-resetting.
  At the moment, configure this pin as gpio-hog to avoid breaking by
  resetting.

- This model has 2x Microchip TCN75A thermal sensors. Linux Kernel
  supports TCN75 chip on lm75 driver, but no support for TCN75'A'
  variant.
  At the moment, use TCN75 support for the chips instead.

Back to the stock firmware:

1. Delete "loadaddr" variable and set "bootcmd" to the original value

   on U-Boot:

     setenv loadaddr
     setenv bootcmd 'ffsrdm c:/runtime.had 0x81000000;alphadec c:/runtime.had 0x81000240 0x80010000;'

   on OpenWrt:

     fw_setenv loadaddr
     fw_setenv bootcmd 'ffsrdm c:/runtime.had 0x81000000;alphadec c:/runtime.had 0x81000240 0x80010000;'

2. Perform reset or reboot

  on U-Boot:

    reset

  on OpenWrt:

    reboot

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-08-06 14:39:57 +02:00
INAGAKI Hiroshi
4974ee7341 realtek: enable pca953x GPIO driver for rtl839x subtarget
The system status LED on Panasonic Switch-M48eG PN28480K is connected to
a PCA9539PW. To use the LED as a status LED of OpenWrt while booting,
enable the pca953x driver and built-in to the kernel.
Also enable CONFIG_GPIO_PCA953X_IRQ to use interrupt via RTL83xx GPIO.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-08-06 14:39:57 +02:00
INAGAKI Hiroshi
fa52e5e254 realtek: add support for Panasonic Switch-M24eG PN28240K
Panasonic Switch-M24eG PN28240K is a 24 + 2 port gigabit switch, based on
RTL8382M.

Specification:

- SoC           : Realtek RTL8382M
- RAM           : DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash         : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet      : 10/100/1000 Mbps x24 + 2
  - port  1-8   : TP, RTL8218B
  - port  9-16  : TP, RTL8218B (SoC)
  - port 17-24  : RTL8218FB
    - port 17-22: TP
    - port 23-24: TP/SFP (Combo)
- LEDs/Keys     : 7x / 1x
- UART          : RS-232 port on the front panel (connector: RJ-45)
  - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
  - 9600n8
- Power         : 100-240 VAC, 50/60 Hz, 0.5 A
  - Plug        : IEC 60320-C13
- Stock OS      : VxWorks based

Flash instruction using initramfs image:

1.  Prepare the TFTP server with the IP address 192.168.1.111
2.  Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
    the TFTP directory
3.  Download the official upgrading firmware (ex: pn28240k_v30000.rom)
    and place it to the TFTP directory
4.  Boot M24eG and interrupt the U-Boot with Ctrl + C keys
5.  Execute the following commands and boot with the OpenWrt initramfs
    image

    rtk network on
    tftpboot 0x81000000
    bootm

6.  Backup mtdblock files to the computer by scp or anything and reboot
7.  Interrupt the U-Boot and execute the following commands to re-create
    filesystem in the flash

    ffsmount c:/
    ffsfmt c:/

    this step takes a long time, about ~ 4 mins

8.  Execute the following commands to put the official images to the
    filesystem

    updatert <official image>

    example:

      updatert pn28240k_v30000.rom

    this step takes about ~ 40 secs

9.  Set the environment variables of the U-Boot by the following commands

    setenv loadaddr 0xb4e00000
    setenv bootcmd bootm
    saveenv

10: Download the OpenWrt initramfs image and boot with it

    tftpboot 0x81000000 0101A8C0.img
    bootm

11: On the initramfs image, download the sysupgrade image and perform
    sysupgrade with it

    sysupgrade <imagename>

12: Wait ~ 120 seconds to complete flashing

Known Issues:

- 2x SFP ports are provided as combo ports by the RTL8218FB chip, but the
  phy driver has no support for it. Currently, only TP ports work by the
  RTL8218D support.

Note:

- "Switch-M24eG" is a model name, and "PN28240K" is a model number.
  Switch-M24eG has an another (old) model number ("PN28240"), it's not a
  Realtek based hardware.

- Switch-M24eG has a "POWER" LED (Green), but it's not connected to any
  GPIO pin.

- U-Boot checks the runtime images in the flash when booting and fails
  to execute "bootcmd" variable if the images are not existing.

- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
  firmware and it includes the stock images, configuration files and
  checksum files. It's unknown format, can't be managed on the OpenWrt.
  To get the enough space for OpenWrt, move the filesystem to the head
  of "fs_reserved" partition by execution of "ffsfmt" and "updatert".

- A GPIO pin on PCA9539 is used for resetting external RTL8218B phy and
  RTL8218FB phy.
  This should be specified as "reset-gpios" property in MDIO node, but
  the current configuration of RTL8218B phy in the phy driver seems to
  be incomplete and RTL8218FB won't be configured on RTL8218D support.
  So, ethernet ports on these phys will be broken after hard-resetting.
  At the moment, configure this pin as gpio-hog to avoid breaking by
  resetting.

Back to the stock firmware:

1. Delete "loadaddr" variable and set "bootcmd" to the original value

   on U-Boot:

     setenv loadaddr
     setenv bootcmd 'bootm 0x81000000'

   on OpenWrt:

     fw_setenv loadaddr
     fw_setenv bootcmd 'bootm 0x81000000'

2. Perform reset or reboot

  on U-Boot:

    reset

  on OpenWrt:

    reboot

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-08-06 14:39:57 +02:00
INAGAKI Hiroshi
3d669ec9cd realtek: add support for Panasonic Switch-M16eG PN28160K
Panasonic Switch-M16eG PN28160K is a 16 + 2 port gigabit switch, based on
RTL8382M.

Specification:

- SoC           : Realtek RTL8382M
- RAM           : DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash         : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet      : 10/100/1000 Mbps x16 + 2
  - port 1-8    : TP, RTL8218B (SoC)
  - port 9-16   : RTL8218FB
    - port  9-14: TP
    - port 15-16: TP/SFP (Combo)
- LEDs/Keys     : 7x / 1x
- UART          : RS-232 port on the front panel (connector: RJ-45)
  - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
  - 9600n8
- Power         : 100-240 VAC, 50/60 Hz, 0.5 A
  - Plug        : IEC 60320-C13
- Stock OS      : VxWorks based

Flash instruction using initramfs image:

1.  Prepare the TFTP server with the IP address 192.168.1.111
2.  Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
    the TFTP directory
3.  Download the official upgrading firmware (ex: pn28160k_v30003.rom)
    and place it to the TFTP directory
4.  Boot M16eG and interrupt the U-Boot with Ctrl + C keys
5.  Execute the following commands and boot with the OpenWrt initramfs
    image

    rtk network on
    tftpboot 0x81000000
    bootm

6.  Backup mtdblock files to the computer by scp or anything and reboot
7.  Interrupt the U-Boot and execute the following commands to re-create
    filesystem in the flash

    ffsmount c:/
    ffsfmt c:/

    this step takes a long time, about ~ 4 mins

8.  Execute the following commands to put the official images to the
    filesystem

    updatert <official image>

    example:

      updatert pn28160k_v30003.rom

    this step takes about ~ 40 secs

9.  Set the environment variables of the U-Boot by the following commands

    setenv loadaddr 0xb4e00000
    setenv bootcmd bootm
    saveenv

10: Download the OpenWrt initramfs image and boot with it

    tftpboot 0x81000000 0101A8C0.img
    bootm

11: On the initramfs image, download the sysupgrade image and perform
    sysupgrade with it

    sysupgrade <imagename>

12: Wait ~ 120 seconds to complete flashing

Known Issues:

- 2x SFP ports are provided as combo ports by the RTL8218FB chip, but the
  phy driver has no support for it. Currently, only TP ports work by the
  RTL8218D support.

Note:

- "Switch-M16eG" is a model name, and "PN28160K" is a model number.
  Switch-M16eG has an another (old) model number ("PN28160"), it's not a
  Realtek based hardware.

- Switch-M16eG has a "POWER" LED (Green), but it's not connected to any
  GPIO pin.

- U-Boot checks the runtime images in the flash when booting and fails
  to execute "bootcmd" variable if the images are not existing.

- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
  firmware and it includes the stock images, configuration files and
  checksum files. It's unknown format, can't be managed on the OpenWrt.
  To get the enough space for OpenWrt, move the filesystem to the head
  of "fs_reserved" partition by execution of "ffsfmt" and "updatert".

- A GPIO pin on PCA9539 is used for resetting external RTL8218FB phy.
  This should be specified as "reset-gpios" property in MDIO node, but
  RTL8218FB won't be configured on RTL8218D support in the phy driver.
  So, ethernet ports on the phy will be broken after hard-resetting.
  At the moment, configure this pin as gpio-hog to avoid breaking by
  resetting.

Back to the stock firmware:

1. Delete "loadaddr" variable and set "bootcmd" to the original value

   on U-Boot:

     setenv loadaddr
     setenv bootcmd 'bootm 0x81000000'

   on OpenWrt:

     fw_setenv loadaddr
     fw_setenv bootcmd 'bootm 0x81000000'

2. Perform reset or reboot

  on U-Boot:

    reset

  on OpenWrt:

    reboot

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-08-06 14:39:57 +02:00
Olliver Schinagl
943905b0b6 realtek: Fix typo in Kconfig prompt
As the symbol RTL930x shows, the bool enables the RTL930x platform, not
the RTL839x one.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
(slightly changed commit subject)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2022-08-05 14:10:42 +02:00
Daniel Golle
a49212d762 Revert "realtek: remove support for HPE 1920 series"
This reverts commit a63aeaecf1.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-07-28 16:45:19 +02:00
Sander Vanheule
a63aeaecf1 realtek: remove support for HPE 1920 series
Support for HPE 1920 images depends on two non-existent tools (mkh3cimg
and mkh3cvfs) from the in the firmware-utils package. Revert commit
f2f09bc002 ("realtek: add support for HPE 1920 series") until support
for these tools is merged and made available in OpenWrt.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-28 15:17:04 +02:00
Jan Hoffmann
f2f09bc002 realtek: add support for HPE 1920 series
Hardware information:
---------------------

- HPE 1920-8G:
  - RTL8380 SoC
  - 8 Gigabit RJ45 ports (built-in RTL8218B)
  - 2 SFP ports (built-in SerDes)

- HPE 1920-16G / HPE 1920-24G (same board):
  - RTL8382 SoC
  - 16/24 Gigabit RJ45 ports (built-in RTL8218B, 1/2 external RTL8218D)
  - 4 SFP ports (external RTL8214FC)

- Common:
  - RJ45 RS232 port on front panel
  - 32 MiB NOR Flash
  - 128 MiB DDR3 DRAM
  - PT7A7514 watchdog

Booting initramfs image:
------------------------

- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
  connect the server to a switch port.

- Connect to the console port of the device and enter the extended
  boot menu by typing Ctrl+B when prompted.

- Choose the menu option "<3> Enter Ethernet SubMenu".

- Set network parameters via the option "<5> Modify Ethernet Parameter".
  Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
  can be left blank, it is not required for booting from RAM). Note that
  the configuration is saved on flash, so it only needs to be done once.

- Select "<1> Download Application Program To SDRAM And Run".

Initial installation:
---------------------

- Boot an initramfs image as described above, then use sysupgrade to
  install OpenWrt permanently. After initial installation, the
  bootloader needs to be configured to load the correct image file

- Enter the extended boot menu again and choose "<4> File Control",
  then select "<2> Set Application File type".

- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
  use the option "<1> +Main" to select it as boot image.

- Choose "<0> Exit To Main Menu" and then "<1> Boot System".

NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-07-28 14:08:56 +02:00
Jan Hoffmann
81e3017609 realtek: clean up rtl838x MDIO busy wait loop
Don't use udelay to allow other kernel tasks to execute if the kernel
has been built without preemption. Also determine the timeout based on
jiffies instead of loop iterations.

This is especially important on devices containing a watchdog with a
short timeout. Without this change, the watchdog is not serviced during
PHY patching which can take multiple seconds.

Tested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-07-28 14:08:51 +02:00
Jan Hoffmann
b6a0d50b7f realtek: add SFP support for RTL8214FC PHY
Probe the SFP module during PHY initialization and implement
insertion/removal handlers to automatically configure the media type
of the respective port.

Suggested-by: Birger Koblitz <git@birger-koblitz.de>
Tested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-07-28 14:08:43 +02:00
Jan Hoffmann
c6a7ea9f7f realtek: rtl83xx-phy: decouple RTL8214FC media change and power config
Move RTL8214FC power configuration to newly created suspend and resume
methods. A media change now only results in power configuration if the
PHY is not suspended, to avoid powering up a port when the interface is
currently not up.

While at it, remove the rtl8380 prefix from function names, as this is
actually not SoC-specific.

Tested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-07-28 14:08:07 +02:00
Jan Hoffmann
bac50e39a7 realtek: rtl83xx-phy: fix RTL8214FC media change
Toggle power on the individual PHY instead of the package. Otherwise
a media change always toggles power on the first port, and not the one
that is being configured.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-07-28 14:07:10 +02:00
Markus Stockhausen
b2681e584c realtek: make DGS-1210 u-boot-env partition writeable
We are close to provide enduser friendly OpenWrt images for DGS-1210
switches that do not need serial console. Nevertheless a small bit is
missing. We cannot switch back to the vendor partition or initiate a
download of a vendor firmware image. To issue this from inside OpenWrt
we need write access to U-Boot environment.

Case 1: Switch back to secondary (vendor) image
> fw_setenv bootcmd run addargs\; bootm 0xb4e80000
> fw_setenv image /dev/mtdblock7
> reboot

Case 2: Issue D-Link Network Assistant based download on next reboot.
This is a combination of some vendor specific protocol (DDP) and a
TFTP download afterwards.
> fw_setenv bootstop on
> reboot

Allow these commands by opening up u-boot-env for write access.
Tested on DGS-1210-20.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-07-26 09:15:38 +02:00
Sander Vanheule
a3e4949998 realtek: clear spurious GPIO interrupts
The interrupt controller in the internal GPIO peripheral will sometimes
generate spurious interrupts. If these are not properly acknowledged, the
system will be held busy until reboot. These spurious interrupts are identified
by the fact that there is no system IRQ number associated, since the interrupt
line was never allocated. Although most prevalent on RTL839x, RTL838x SoCs have
also displayed this behaviour.

Reported-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> # DGS-1210-52
Reported-by: Birger Koblitz <mail@birger-koblitz.de> # Netgear GS724TP v2
Reported-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-16G
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-21 22:44:01 +02:00
Sander Vanheule
1773264a0c realtek: correct egress frame port verification
Destination switch ports for outgoing frame can range from 0 to
CPU_PORT-1.

Refactor the code to only generate egress frame CPU headers when a valid
destination port number is available, and make the code a bit more
consistent between different switch generations. Change the dest_port
argument's type to 'unsigned int', since only positive values are valid.

This fixes the issue where egress frames on switch port 0 did not
receive a VLAN tag, because they are sent out without a CPU header.
Also fixes a potential issue with invalid (negative) egress port numbers
on RTL93xx switches.

Reported-by: Arınç ÜNAL <arinc.unal@xeront.com>
Suggested-by: Birger Koblitz <mail@birger-koblitz.de>
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-17 10:06:51 +02:00
Sander Vanheule
0b35a08a05 realtek: correct egress frame priority assignment
Priority values passed to the egress (TX) frame header initialiser are
invalid when smaller than 0, and should not be assigned to the frame.
Queue assignment is then left to the switch core logic.

Current code for RTL83xx forces the passed priority value to be
positive, by always masking it to the lower bits, resulting in the
priority always being set and enabled. RTL93xx code doesn't even check
the value and unconditionally assigns the (32 bit) value to the (5 bit)
QID field without masking.

Fix priority assignment by only setting the AS_QID/AS_PRI flag when a
valid value is passed, and properly mask the value to not overflow the
QID/PRI field.

For RTL839x, also assign the priority to the right part of the frame
header. Counting from the leftmost bit, AS_PRI and PRI are in bits 36
and 37-39. The means they should be assigned to the third 16 bit value,
containing bits 32-47.

Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-17 10:06:46 +02:00
Sander Vanheule
d6165ea75b realtek: fix egress L2 learning on rtl839x
The flag to enable L2 address learning on egress frames is in CPU header
bit 40, with bit 0 being the leftmost bit of the header. This
corresponds to BIT(7) in the third 16-bit value of the header.

Correctly set L2LEARNING by fixing the off-by-one error.

Fixes: 9eab76c84e ("realtek: Improve TX CPU-Tag usage")
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-17 10:06:40 +02:00
Sander Vanheule
d9516cacb0 realtek: fix egress port mask on rtl839x
The flag to enable the outgoing port mask is in CPU header bit 43, with
bit 0 being the leftmost bit of the header. This corresponds to BIT(4)
in the third 16-bit value of the header.

Correctly set AS_DPM by fixing the off-by-one error.

Fixes: 9eab76c84e ("realtek: Improve TX CPU-Tag usage")
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-17 10:06:32 +02:00
Sander Vanheule
eae5e55a79 realtek: remove hardcoded sys-led configurations
setup.c unconditionally sets the sys-led mode (blinking rate) to a
permanent high output. This may cause issues when a board expects this
pin to toggle periodically, e.g. when hooked up to an external watchdog.

If the sys-led peripheral is used to control an LED, the mux should be
configured to use the pin as GPIO0, allowing for better control as a
GPIO LED.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-10 09:54:35 +02:00
Sander Vanheule
b03109c094 realtek: add mux pinctrl for rtl931x
Add a pinctrl-single node to manage the sys-led mux and JTAG mux.
This allows using the associated pins as GPIOs:
  - sys-led: GPIO0
  - JTAG: GPIO6, GPIO7, others unknown (TDO, TDI, TMS, TCK /TRST)

Suggested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-10 09:54:35 +02:00
Sander Vanheule
3edb5e841c realtek: add system LED for ZyXEL XGS1250-12
The devicetree for the ZyXEL XGS1250-12 was missing the description of
the front panel LED labeled "PWR SYS". Let's add it so it can be
controlled by the user.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-10 09:54:35 +02:00
Sander Vanheule
cd7a225d28 realtek: add sys-led disable pinctrl for rtl930x
Like for RTL838x devices, add a pinctrl-single node to manage the
sys-led/gpio0 mux, and allow using the pin as GPIO.

Co-developed-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-10 09:54:35 +02:00
Sander Vanheule
f4065485d3 realtek: add missing gpio0 pinctrl properties
Not all devices using the gpio0/sys-led pin as a GPIO, configure the
pinmux. Add the necessary pinctrl properties to these devices to ensure
the pin is set up for use as GPIO.

Co-developed-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Bjørn Mork <bjorn@mork.no>
2022-07-10 09:54:35 +02:00
Markus Stockhausen
fae3ac3560 realtek: build sane factory images for DGS-1210 models
During upload of firmware images the WebUI and CLI patch process
extracts a version information from the uploaded file and stores it
onto the jffs2 partition. To be precise it is written into the
flash.txt or flash2.txt files depending on the selected target image.
This data is not used anywhere else. The current OpenWrt factory
image misses this label. Therefore version information shows only
garbage. Fix this.

Before:
DGS-1210-20> show firmware information
IMAGE ONE:
Version      : xfo/QE~WQD"A\Scxq...
Size         : 5505185 Bytes

After:
DGS-1210-20> show firmware information
IMAGE ONE:
Version      : OpenWrt
Size         : 5505200 Bytes

Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-07-08 20:15:22 +02:00
Markus Stockhausen
2b49ec3a28 realtek: build factory images for all DGS-1210 models
Currently we build factory images only for DGS-1210-28 model. Relax
that constraint and take care about all models. Tested on DGS-1210-20
and should work on other models too because of common flash layout.

Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-07-08 20:15:22 +02:00
Luiz Angelo Daros de Luca
8b798dbb39 realtek: rename u-boot-env2 to board-name
Some realtek boards have two u-boot-env partitions. However, in the
DGS-1210 series, the mtdblock2 partition is not a valid u-boot env
and simply contains the board/device name, followed by nulls.

00000000  44 47 53 2d 31 32 31 30  2d 32 38 2d 46 31 00 00 |DGS-1210-28-F1..|
00000010  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00 |................|
*
00040000

00000000  44 47 53 2d 31 32 31 30  2d 35 32 2d 46 31 00 00 |DGS-1210-52-F1..|
00000010  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00 |................|
*
00040000

The misleading u-boot-env2 name also confuses uboot-envtools.

Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
2022-07-05 21:52:14 +02:00
Markus Stockhausen
e763c4c89f realtek: build DGS-1210 images with CAMEO tag
From now on we will insert CAMEO tags into sysupgrade images for
DGS-1210 devices. This will make the "OS:...FAILED" and "FS:...FAILED"
messages go away.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-07-05 09:56:37 +02:00
Alexandru Gagniuc
36acb3db03 realtek: EnGenius EWS2910P: declare and hog the poe-enable GPIO
GPIO 1 on the RTL8231 is used to force the PoE MCU to disable power
outputs. It is not used by any driver, but if accidentally set low,
PoE outputs are disabled. This situation is hard to debug, and
requires knowledge of the Broadcom PoE protocol used by the MCU.

To prevent this situation, hog it as an output high. This is
consistent with the ZyXel GS1900 series handles it.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-07-02 11:50:47 +02:00
Luiz Angelo Daros de Luca
1005dc0a64 realtek: add DGS-1210-28 factory image
DGS-1210 switches support dual image, with each image composed of a
kernel and a rootfs partition. For image1, kernel and rootfs are in
sequence. The current OpenWrt image (written using a serial console),
uses those partitions together as the firmware partition, ignoring the
partition division. The current OEM u-boot fails to validate image1 but
it will only trigger firmware recovery if both image1 and image2 fail,
and it does not switch the boot image in case one of them fails the
check.

The OEM factory image is composed of concatenated blocks of data, each
one prefixed with a 0x40-byte cameo header. A normal OEM firmware will
have two of these blocks (kernel, rootfs). The OEM firmware only checks
the header before writing unconditionally the data (except the header)
to the correspoding partition.

The OpenWrt factory image mimics the OEM image by cutting the
kernel+rootfs firmware at the exact size of the OEM kernel partition
and packing it as "the kernel partition" and the rest of the kernel and
the rootfs as "the rootfs partition". It will only work if written to
image1 because image2 has a sysinfo partition between kernel2 and
rootfs2, cutting the kernel code in the middle.

Steps to install:

1) switch to image2 (containing an OEM image), using web or these CLI
   commands:
   - config firmware image_id 2 boot_up
   - reboot
2) flash the factory_image1.bin to image1. OEM web (v6.30.016)
   is crashing for any upload (ssh keys, firmware), even applying OEM
   firmwares. These CLI commands can upload a new firmware to the other
   image location (not used to boot):
   - download firmware_fromTFTP <tftpserver> factory_image1.bin
   - config firmware image_id 1 boot_up
   - reboot

To debrick the device, you'll need serial access. If you want to
recover to an OpenWrt, you can replay the serial installation
instructions. For returning to the original firmware, press ESC during
the boot to trigger the emergency firmware recovery procedure. After
that, use D-Link Network Assistant v2.0.2.4 to flash a new firmware.

The device documentation does describe that holding RESET for 12s
trigger the firmware recovery. However, the latest shipped U-Boot
"2011.12.(2.1.5.67086)-Candidate1" from "Aug 24 2021 - 17:33:09" cannot
trigger that from a cold boot. In fact, any U-Boot procedure that relies
on the RESET button, like reset settings, will only work if started from
a running original firmware. That, in practice, cancels the benefit of
having two images and a firmware recovery procedure (if you are not
consider dual-booting OpenWrt).

Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
2022-06-28 22:20:09 +02:00
Markus Stockhausen
78b7be9f6c realtek: cleanup LAG logging
Setting up DSA bond silently fails if mode is not 802.3ad. Add log message
to fix it. As we are already here harmonize all logging messages in the
add/delete functions.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-06-26 11:02:15 +02:00
Alexandru Gagniuc
4d1fc8916c realtek: EnGenius EWS2910P: add support for SFP ports
The SFP cages 9F and 10F share the same SCL line. Currently, there
isn't a good way to model this. Thus, only one SFP port can be fully
supported.

Cage 10F is fully supported with an I2C bus and sfp handle. Linux
automatically handles enabling or disabling the TX laser.

Cage 9F is only parially supported, without the sfp handle. The SDA
line is hogged as an input, so that it remains high. SCL transitions
sould not affect modules connected to this cage. The default value of
the tx-disable line is high (active). It is exported as a gpio, but
the laser is off by default. To enable the laser:

    echo 0 > /sys/class/gpio/sff-p9-tx-disable/value

Thus, both modules can be used for networking, but only 10F will be
able to detect and identify a plugged in SFP module.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-06-25 15:45:30 +02:00
Alexandru Gagniuc
2cfaab4549 realtek: add support for EnGenius EWS2910P
Add support for the Engenius EWS2910P PoE switch. This is an RTL8380
based switch with two SFP slots, and PoE 802.3af one every RJ-45 port.

The specs say 802.3af, but the vendor firmware configures the PSE for
a budget of 31W, indicating 802.3at support.

Specifications:
---------------
* SoC:       Realtek RTL8380M
* Flash:     32 MiB SPI flash Macronix MX25L25635E
* RAM:       256 MiB (As reported by bootloader)
* Ethernet:  16x 10/100/1000 Mbps with PoE
              2x SFP slots
* Buttons:   1 "Reset" button on front panel
             1 "LED mode: button on front panel
             1 "On/Off" Toggle switch on the back
* Power:     48V-54V DC barrel jack
* UART:      1 serial header (JP1) with populated 2.54mm pitch header
             Labeled GRTV for ground, rx, tx, and 3.3V respectively
* PoE:       1 STM ST32F100 microcontroller
             2 BCM59111 PSE chips
Works:
------
  - (8) RJ-45 ethernet ports
  - Switch functions
  - LEDs and buttons

Not yet enabled:
----------------
  - SFP ports (will be enabled in a subsequent change)
  - Power-over-Ethernet (requires realtek-poe package)

Install via web interface:
-------------------------

The factory firmware will accept and flash the initramfs image. It is
recommended to flash to "Partition 0". Flashing to "Partition 1" is
not supported at this point.

The factory web GUI will show the following warning:

 " Warning: The firmware version is v0.00.00-c0.0.00
     The firmware image you are uploading is older than the current
     firmware of the switch. The device will reset back to default
     settings. Are you sure you want to proceed?"

This is expected when flashing OpenWrt. After the initramfs image
boots, flash the -sysupgrade using either the commandline or LuCI.

Install via serial console/tftp:
--------------------------------

The u-boot firmware will not stop the boot, regardless of which key is
pressed. To access the u-boot console, ground out the CLK (pin 16) of
the ROM (U22) when u-boot is reading the linux image. If timed
correctly, the image CRC will fail, and u-boot will drop to a shell:
    > rtk network on
    > setenv ipaddr <address of tftp server>
    > tftp $(freemem) <name-of-initramfs-image.bin>
    > bootm

Then flash the -sysupgrade using either the commandline or luci.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[gpio-led node names, OpenWrt and LuCI capitalization in commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-06-25 15:43:46 +02:00
Tomasz Maciej Nowak
539e60539a generic: enable CRYPTO_LIB_BLAKE2S[_X86|_ARM]
This is now built-in, enable so it won't propagate on target configs.

Link: https://lkml.org/lkml/2022/1/3/168
Fixes: 79e7a2552e ("kernel: bump 5.15 to 5.15.44")
Fixes: 0ca9367069 ("kernel: bump 5.10 to 5.10.119")
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
(Link to Kernel's commit taht made it built-in,
CRYPTO_LIB_BLAKE2S[_ARM|_X86] as it's selectable, 5.10 backport)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2022-06-24 17:10:24 +02:00
Bjørn Mork
d6eebaf995 realtek: fix gcc-12 build with -Werror=array-compare
Removing this gcc-12 error:

arch/mips/rtl838x/setup.c:64:30: error: comparison between two arrays [-Werror=array-compare]
   64 |         else if (__dtb_start != __dtb_end)

Signed-off-by: Bjørn Mork <bjorn@mork.no>
2022-06-22 18:37:40 +02:00
Andreas Böhler
d9e12c21fa realtek: make "u-boot-env" partition writable for Netgear 3xx series
The Netgear GS3xx devices do not properly initialise the port LEDs during
startup unless the boot command in U-Boot is changed. Making the U-Boot
env partition writable allows this modification to be done from within
OpenWrt by calling "fw_setenv bootcmd rtk network on\; boota".

Signed-off-by: Andreas Böhler <dev@aboehler.at>
2022-06-22 17:52:30 +02:00
Stijn Segers
9c381d3386 realtek: make Netgear GS1xx u-boot env partition writable
Make the u-boot environment partition for the NETGEAR
GS108T v3 and GS110TPP writable (they share a DTS), so
the values can be manipulated from userspace.

See https://forum.openwrt.org/t/57875/1567 for a real
world example.

Signed-off-by: Stijn Segers <foss@volatilesystems.org>
2022-06-22 17:51:02 +02:00
Pascal Ernster
adbdfc9366 realtek: add support for power LED on Netgear GS108Tv3
The Netgear GS108Tv3 is already supported by OpenWrt, but is missing LED
support. After OpenWrt installation, all LEDs are off which makes the
installation quite confusing.
This enables support for the green/amber power LED to give feedback
about the current status.

This is basically just a verbatim copy of commit c4927747d2 ("realtek:
add support for power LED on Netgear GS308Tv1").

Please note that both LEDs are wired up in an anti-parallel fashion,
which means that only one of both LEDs/colors can be switched on at the
same time. If both LEDs/colors are switched on simultanously, the LED
goes dark.

Tested-by: Pascal Ernster <git@hardfalcon.net>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
[add title to commit reference]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-06-19 10:58:40 +02:00
Markus Stockhausen
6153c530cc realtek: add support for D-Link DGS-1210-20
Hardware specification
 ----------------------

 * RTL8382M SoC, 1 MIPS 4KEc core @ 500MHz
 * 128MB DRAM
 * 32MB NOR Flash
 * 16 x 10/100/1000BASE-T ports
    - Internal PHY with 8 ports (RTL8218B)
    - External PHY with 8 ports (RTL8218B)
 * 4 x Gigabit RJ45/SFP Combo ports
    - External PHY with 4 SFP ports (RTL8214FC)
 * Power LED
 * Reset button on front panel
 * UART (115200 8N1) via unpopulated standard 0.1" pin header marked J6

 UART pinout
 -----------

  [o]ooo|J6
   | ||`------ GND
   | |`------- RX
   | `-------- TX
   `---------- Vcc (3V3)

 Boot initramfs image from U-Boot
 --------------------------------

  1. Press Escape key during `Hit Esc key to stop autoboot` prompt
  2. Press CTRL+C keys to get into real U-Boot prompt
  3. Init network with `rtk network on` command
  4. Load image with `tftpboot 0x8f000000 openwrt-realtek-rtl838x-d-link_dgs-1210-20-initramfs-kernel.bin` command
  5. Boot the image with `bootm` command

To install, upload the sysupgrade image to the OEM webpage or sysupgrade
from the system running from initramfs image.

It has been developed and tested on device with F1 revision.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct initramfs image name]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-06-19 08:36:21 +02:00
Andreas Böhler
c4927747d2 realtek: add support for power LED on Netgear GS308Tv1
The Netgear GS308Tv1 is already supported by OpenWrt, but is missing LED
support. After OpenWrt installation, all LEDs are off which makes the
installation quite confusing.
This enables support for the green/amber power LED to give feedback
about the current status.

Signed-off-by: Andreas Böhler <dev@aboehler.at>
2022-06-18 09:21:50 +02:00
Luiz Angelo Daros de Luca
f5a87a0a7b realtek: add gpio-restart for D-Link DGS-1210-28
A GPIO assert is required to reset the system. Otherwise, the system
will hang on reboot.

Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Reviewed-by: Robert Marko <robimarko@gmail.com>
2022-06-07 17:11:28 +02:00
Luiz Angelo Daros de Luca
8121e7dd75 realtek: add reset button for D-Link DGS-1210-28
Tested in a DGS-1210-28 F3, both triggering failsafe and reboot.

Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Reviewed-by: Robert Marko <robimarko@gmail.com>
2022-06-07 17:11:28 +02:00
John Audia
f800f8d6fc kernel: bump 5.10 to 5.10.120
All patches automatically rebased.

Build system: x86_64
Build-tested: ipq806x/R7800, x86/64

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-06-06 19:20:02 +02:00
John Audia
cd634afe6c kernel: bump 5.10 to 5.10.119
Delete the crypto-lib-blake2s kmod package, as BLAKE2s is now built-in.
Patches automatically rebased.

Build system: x86_64
Build-tested: ipq806x/R7800, x86/64

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-06-06 19:20:02 +02:00
Raylynn Knight
b515ad10a6 realtek: add support for ZyXEL GS1900-24E
The ZyXEL GS1900-24E is a 24 port gigabit switch similar to other GS1900
switches.

Specifications
--------------
* Device:    ZyXEL GS1900-24E
* SoC:       Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash:     16 MiB Macronix MX25L12835F
* RAM:       128 MiB DDR2 SDRAM Nanya NT5TU128M8GE
* Ethernet:  24x 10/100/1000 Mbps
* LEDs:      1 PWR LED (green, not configurable)
             1 SYS LED (green, configurable)
             24 ethernet port link/activity LEDs (green, SoC controlled)
* Buttons:   1 "RESET" button on front panel
* Switch:    1 Power switch on rear of device
* Power      120-240V AC C13
* UART:      1 serial header (JP2) with populated standard pin connector on
             the left side of the PCB.
             Pinout (front to back):
             + Pin 1 - VCC marked with white dot
             + Pin 2 - RX
             + Pin 3 - TX
             + PIn 4 - GND

Serial connection parameters:  115200 8N1.

Installation
------------

OEM upgrade method:

* Log in to OEM management web interface
* Navigate to Maintenance > Firmware
* Select the HTTP radio button
* Select the Active radio button
* Use the browse button to locate the
realtek-rtl838x-zyxel_gs1900-24e-initramfs-kernel.bin
file and select open so File Path is updated with filename.
* Select the Apply button. Screen will display "Prepare
for firmware upgrade ...".
*Wait until screen shows "Do you really want to reboot?"
then select the OK button
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
   > sysupgrade -n /tmp/realtek-rtl838x-zyxel_gs1900-24e-squashfs-sysupgrade.bin
   it may be necessary to restart the network (/etc/init.d/network restart) on
   the running initramfs image.

U-Boot TFTP method:

* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).
* Set up a TFTP server on your client and make it serve the initramfs image.
* Connect serial, power up the switch, interrupt U-boot by hitting the
  space bar, and enable the network:
   > rtk network on
* Since the GS1900-24E is a dual-partition device, you want to keep the OEM
  firmware on the backup partition for the time being. OpenWrt can only boot
  from the first partition anyway (hardcoded in the DTS). To make sure we are
  manipulating the first partition, issue the following commands:
  > setsys bootpartition 0
  > savesys
* Download the image onto the device and boot from it:
   > tftpboot 0x84f00000 192.168.1.10:openwrt-realtek-rtl838x-zyxel_gs1900-24e-initramfs-kernel.bin
   > bootm
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
   > sysupgrade -n /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24e-squashfs-sysupgrade.bin
   it may be necessary to restart the network (/etc/init.d/network restart) on
   the running initramfs image.

Signed-off-by: Raylynn Knight <rayknight@me.com>
2022-06-06 10:30:50 +02:00
Sander Vanheule
bde6311569 realtek: don't unmask non-maskable GPIO IRQs
On uniprocessor builds, for_each_cpu(cpu, mask) will assume 'mask'
always contains exactly one CPU, and ignore the actual mask contents.
This causes the loop to run, even when it shouldn't on an empty mask,
and tries to access an uninitialised pointer.

Fix this by wrapping the loop in a cpumask_empty() check, to ensure it
will not run on uniprocessor builds if the CPU mask is empty.

Fixes: af6cd37f42 ("realtek: replace RTL93xx GPIO patches")
Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Reported-by: Robert Marko <robimarko@gmail.com>
Tested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-05-30 07:21:03 +02:00
Sander Vanheule
af6cd37f42 realtek: replace RTL93xx GPIO patches
Patches to support the SoC's GPIO controller for RTL930x and RTL931x
devices have been accepted upstream. Replace the current preliminary
patch with the upstream ones, excluding devictree binding changes.

The updated patches add GPIO IRQ balancing support on RTL930x, but this
cannot be used until these devices also support SMP.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-05-22 08:46:50 +02:00
Tony Ambardar
76fae1d169 config: limit CONFIG_DEBUG_INFO to top-level generic configs
Remove redundant target-level entries, noting that these settings will be
configured from "Kernel build options" of Kconfig.

Signed-off-by: Tony Ambardar <itugrok@yahoo.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
[remove from new configs introduced after patch submission]
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-05-18 13:32:06 +03:00
John Audia
8592df67f4 kernel: bump 5.10 to 5.10.114
All patches automatically rebased.

Build system: x86_64
Build-tested: bcm2711/RPi4B
Run-tested: bcm2711/RPi4B

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-05-16 20:26:38 +02:00
Birger Koblitz
d1b824650f realtek: do not reset SerDes on link change
Do not reset the RTL930x SerDes on link changes, instead set up
the SDS with internal PHYs for the SFP+ ports only.
This fixes the 8 1GBit ports on the Zyxel XGS1250 which
do not work without this patch.

A complete SerDes reset was performed on all SerDes links. For copper
1Gbit ports, this is commonly a single XGMII link to an RTL8218D. There
is however no support for setting up the XGMII link on RTL9300/RTL9310,
thereby wiping the (RX/TX) setup done by u-boot and breaking the 1GBit
ports. No SerDes reset should be done for these links.

The handling of SGMII/HiSGMII, 1000BX or 10GR links is actually entirely
different. All these modes need to be suitably RX calibrated and the
pre- main and post- amplifiers set up properly for TX.

The 10GBit SFP+ fiber links are recalibrated instead of reset, which
e.g. is necessary when someone pulls a module out and puts another in.
This makes swapping out 10GBit fiber modules possible. 1GBit modules are
not yet supported, nor any modules with an internal phy.

Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
[rewrite commit message based on discussion]
Link: http://lists.infradead.org/pipermail/openwrt-devel/2022-May/038623.html
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-05-11 22:23:50 +02:00
Birger Koblitz
98bb26f9f7 realtek: Trap all frames with switch as destination to CPU-port
This fixes a bug where frames sent to the switch itself were
flooded to all ports unless the MAC address of the CPU-port
was learned otherwise.

Tested-by: Wenli Looi <wlooi@ucalgary.ca>
Tested-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
[fix code formatting]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-05-08 10:05:14 +02:00
Raylynn Knight
580723e86a realtek: add support for ZyXEL GS1900-16
The ZyXEL GS1900-16 is a 16 port gigabit switch similar to other GS1900 switches.

Specifications
--------------
* Device:    ZyXEL GS1900-16
* SoC:       Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash:     16 MiB Macronix MX25L12835F
* RAM:       128 MiB DDR2 SDRAM Nanya NT5TU128M8HE
* Ethernet:  16x 10/100/1000 Mbps
* LEDs:      1 PWR LED (green, not configurable)
             1 SYS LED (green, configurable)
             16 ethernet port link/activity LEDs (green, SoC controlled)
* Buttons:   1 "RESET" button on front panel
* Power      120-240V AC C13
* UART:      1 serial header (J12) with populated standard pin connector on
             the right back of the PCB.
             Pinout (front to back):
             + Pin 1 - VCC marked with white dot
             + Pin 2 - RX
             + Pin 3 - TX
             + PIn 4 - GND

Serial connection parameters:  115200 8N1.

Installation
------------

OEM upgrade method:

* Log in to OEM management web interface
* Navigate to Maintenance > Firmware
* Select the HTTP radio button
* Select the Active radio button
* Use the browse button to locate the
realtek-generic-zyxel_gs1900-16-initramfs-kernel.bin
file amd select open so File Path is update with filename.
* Select the Apply button. Screen will display "Prepare
for firmware upgrade ...".
*Wait until screen shows "Do you really want to reboot?"
then select the OK button
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
   > sysupgrade -n /tmp/realtek-generic-zyxel_gs1900-16-squashfs-sysupgrade.bin
   it may be necessary to restart the network (/etc/init.d/network restart) on
   the running initramfs image.

U-Boot TFTP method:

* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).
* Set up a TFTP server on your client and make it serve the initramfs image.
* Connect serial, power up the switch, interrupt U-boot by hitting the
  space bar, and enable the network:
   > rtk network on
* Since the GS1900-16 is a dual-partition device, you want to keep the OEM
  firmware on the backup partition for the time being. OpenWrt can only boot
  from the first partition anyway (hardcoded in the DTS). To make sure we are
  manipulating the first partition, issue the following commands:
  > setsys bootpartition 0
  > savesys
* Download the image onto the device and boot from it:
   > tftpboot 0x84f00000 192.168.1.10:openwrt-realtek-generic-zyxel_gs1900-16-initramfs-kernel.bin
   > bootm
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
   > sysupgrade -n /tmp/openwrt-realtek-generic-zyxel_gs1900-16-squashfs-sysupgrade.bin
   it may be necessary to restart the network (/etc/init.d/network restart) on
   the running initramfs image.

Signed-off-by: Raylynn Knight <rayknight@me.com>
[removed duplicate patch title, align RAM specification]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-05-07 17:23:45 +02:00
Martin Kennedy
a5ac8ad0ba realtek: add ZyXEL GS1900-24HP v1 support
The ZyXEL GS1900-24HP v1 is a 24 port PoE switch with two SFP ports,
similar to the other GS1900 switches.

Specifications
--------------
* Device:    ZyXEL GS1900-24HP v1
* SoC:       Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash:     16 MiB
* RAM:       Winbond W9751G8KB-25 64 MiB DDR2 SDRAM
* Ethernet:  24x 10/100/1000 Mbps, 2x SFP 100/1000 Mbps
* LEDs:
  * 1 PWR LED (green, not configurable)
  * 1 SYS LED (green, configurable)
  * 24 ethernet port link/activity LEDs (green, SoC controlled)
  * 24 ethernet port PoE status LEDs
  * 2 SFP status/activity LEDs (green, SoC controlled)
* Buttons:
  * 1 "RESET" button on front panel (soft reset)
  * 1 button ('SW1') behind right hex grate (hardwired power-off)
* PoE:
  * Management MCU: ST Micro ST32F100 Microcontroller
  * 6 BCM59111 PSE chips
  * 170W power budget
* Power:     120-240V AC C13
* UART:      Internal populated 10-pin header ('J5') providing RS232;
             connected to SoC UART through a TI or SIPEX 3232C for voltage
             level shifting.

* 'J5' RS232 Pinout (dot as pin 1):
  2) SoC RXD
  3) GND
  10) SoC TXD

Serial connection parameters: 115200 8N1.

Installation
------------

OEM upgrade method:

* Log in to OEM management web interface

* Navigate to Maintenance > Firmware > Management

* If "Active Image" has the first option selected, OpenWrt will need to be
  flashed to the "Active" partition. If the second option is selected,
  OpenWrt will need to be flashed to the "Backup" partition.

* Navigate to Maintenance > Firmware > Upload

* Upload the openwrt-realtek-rtl838x-zyxel_gs1900-24hp-v1-initramfs-kernel.bin
  file by your preferred method to the previously determined partition.
  When prompted, select to boot from the newly flashed image, and reboot
  the switch.

* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:

  > sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24hp-v1-squashfs-sysupgrade.bin

U-Boot TFTP method:

* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).

* Set up a TFTP server on your client and make it serve the initramfs
  image.

* Connect serial, power up the switch, interrupt U-boot by hitting the
  space bar, and enable the network:

  > rtk network on

* Since the GS1900-24HP v1 is a dual-partition device, you want to keep the
  OEM firmware on the backup partition for the time being. OpenWrt can
  only be installed in the first partition anyway (hardcoded in the
  DTS). To ensure we are set to boot from the first partition, issue the
  following commands:

  > setsys bootpartition 0
  > savesys

* Download the image onto the device and boot from it:

  > tftpboot 0x81f00000 192.168.1.10:openwrt-realtek-rtl838x-zyxel_gs1900-24hp-v1-initramfs-kernel.bin
  > bootm

* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:

  > sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24hp-v1-squashfs-sysupgrade.bin

Signed-off-by: Martin Kennedy <hurricos@gmail.com>
[Add info on PoE hardware to commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-04-16 17:26:56 +02:00
Hauke Mehrtens
34fb36e165 realtek: Fix tc default package
The tc package does not exits any more, it was split into tc-tiny,
tc-full and tc-bpf. Include tc-bpf by default into realtek images.

This increases the compressed image size by about 232KBytes.

Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2022-03-29 13:43:01 +02:00
Hauke Mehrtens
469030659c realtek: Use firewall4
The realtek target is not a router, but basic device, see DEVICE_TYPE.
The basic device type does not come with firewall by default, see
include/target.mk for details. The realtek target extended
DEFAULT_PACKAGES manually with firewall.

This changes the defaults to take firewall4 and nftables instead of
firewall and iptables. This also adds the additional package
kmod-nft-offload.

The only difference to the router type is the missing ppp,
ppp-mod-pppoe, dnsmasq and odhcpd-ipv6only package.

This increases the compressed image size by about 422KBytes.

Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2022-03-29 13:42:56 +02:00
Hauke Mehrtens
2acebbdcaa realtek: Remove dnsmasq and odhcpd-ipv6only from default
Do not include the dnsmasq and odhcpd-ipv6only package by default any
more. These services are not needed on a switch. If someone needs this
it is still possible to use opkg or image builder to add them.

This decreases the compressed image size by about 165KBytes.

Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2022-03-29 13:42:29 +02:00
John Audia
b04d38a2ea kernel: bump 5.10 to 5.10.106
All patches automatically rebased.

Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200

Signed-off-by: John Audia <graysky@archlinux.us>
2022-03-19 16:13:58 +01:00
INAGAKI Hiroshi
e83ab243be realtek: add support for Panasonic Switch-M8eG PN28080K
Panasonic Switch-M8eG PN28080K is a 8 + 1 port gigabit switch, based on
RTL8380M.

Specification:

- SoC		: Realtek RTL8380M
- RAM		: DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash		: SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet	: 10/100/1000 Mbps x8 + 1
  - port 1-8	: TP, RTL8218B (SoC)
  - port 9	: SFP, RTL8380M (SoC)
- LEDs/Keys	: 7x / 1x
- UART		: RS-232 port on the front panel (connector: RJ-45)
  - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
  - 9600n8
- Power		: 100-240 VAC, 50/60 Hz, 0.5 A
  - Plug	: IEC 60320-C13
- Stock OS	: VxWorks based

Flash instruction using initramfs image:

1.  Prepare the TFTP server with the IP address 192.168.1.111
2.  Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
    the TFTP directory
3.  Download the official upgrading firmware (ex: pn28080k_v30000.rom)
    and place it to the TFTP directory
4.  Boot M8eG and interrupt the U-Boot with Ctrl + C keys
5.  Execute the following commands and boot with the OpenWrt initramfs
    image

    rtk network on
    tftpboot 0x81000000
    bootm

6.  Backup mtdblock files to the computer by scp or anything and reboot
7.  Interrupt the U-Boot and execute the following commands to re-create
    filesystem in the flash

    ffsmount c:/
    ffsfmt c:/

    this step takes a long time, about ~ 4 mins

8.  Execute the following commands to put the official images to the
    filesystem

    updatert <official image>

    example:

      updatert pn28080k_v30000.rom

    this step takes about ~ 40 secs

9.  Set the environment variables of the U-Boot by the following commands

    setenv loadaddr 0xb4e00000
    setenv bootcmd bootm
    saveenv

10: Download the OpenWrt initramfs image and boot with it

    tftpboot 0x81000000 0101A8C0.img
    bootm

11: On the initramfs image, download the sysupgrade image and perform
    sysupgrade with it

    sysupgrade <imagename>

12: Wait ~ 120 seconds to complete flashing

Note:

- "Switch-M8eG" is a model name, and "PN28080K" is a model number.
  Switch-M8eG has an another (old) model number ("PN28080"), it's not a
  Realtek based hardware.

- Switch-M8eG has a "POWER" LED (Green), but it's not connected to any
  GPIO pin.

- The U-Boot checks the runtime images in the flash when booting and
  fails to execute anything in "bootcmd" variable if the images are not
  exsisting.

- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
  firmware and it includes the stock images, configuration files and
  checksum files. It's unknown format, can't be managed on the OpenWrt.
  To get the enough space for OpenWrt, move the filesystem to the head
  of "fs_reserved" partition by execution of "ffsfmt" and "updatert".

- On the other devices in the same series of Switch-M8eG PN28080K, the
  INT pin on the PCA9555 is not connected to anywhere.

Back to the stock firmware:

1. Delete "loadaddr" variable and set "bootcmd" to the original value

   on U-Boot:

     setenv loadaddr
     setenv bootcmd 'bootm 0x81000000'

   on OpenWrt:

     fw_setenv loadaddr
     fw_setenv bootcmd 'bootm 0x81000000'

2. Perform reset or reboot

  on U-Boot:

    reset

  on OpenWrt:

    reboot

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Reviewed-by: Sander Vanheule <sander@svanheule.net>
2022-03-13 19:54:57 +01:00
INAGAKI Hiroshi
da1347d6d6 realtek: enable pca953x driver for rtl838x subtarget
The system status LED on Panasonic Switch-M8eG PN28080K is connected to
a PCA9539PW. To use the LED as a status LED of OpenWrt while booting,
enable the pca953x driver and built-in to the kernel.
Also enable CONFIG_GPIO_PCA953X_IRQ to use interrupt via RTL83xx GPIO.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Acked-by: Sander Vanheule <sander@svanheule.net>
2022-03-13 19:54:57 +01:00
Martin Kennedy
d1a8690742 realtek: add ZyXEL GS1900-24 v1 support
The ZyXEL GS1900-24 v1 is a 24 port switch with two SFP ports, similar to
the other GS1900 switches.

Specifications
--------------
* Device:    ZyXEL GS1900-24 v1
* SoC:       Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash:     16 MiB
* RAM:       Winbond W9751G8KB-25 64 MiB DDR2 SDRAM
* Ethernet:  24x 10/100/1000 Mbps, 2x SFP 100/1000 Mbps
* LEDs:
  * 1 PWR LED (green, not configurable)
  * 1 SYS LED (green, configurable)
  * 24 ethernet port link/activity LEDs (green, SoC controlled)
  * 2 SFP status/activity LEDs (green, SoC controlled)
* Buttons:
  * 1 "RESET" button on front panel (soft reset)
  * 1 button ('SW1') behind right hex grate (hardwired power-off)
* Power:     120-240V AC C13
* UART:      Internal populated 10-pin header ('J5') providing RS232;
             connected to SoC UART through a SIPEX 3232EC for voltage
             level shifting.

* 'J5' RS232 Pinout (dot as pin 1):
  2) SoC RXD
  3) GND
  10) SoC TXD

Serial connection parameters: 115200 8N1.

Installation
------------

OEM upgrade method:

* Log in to OEM management web interface

* Navigate to Maintenance > Firmware > Management

* If "Active Image" has the first option selected, OpenWrt will need to be
  flashed to the "Active" partition. If the second option is selected,
  OpenWrt will need to be flashed to the "Backup" partition.

* Navigate to Maintenance > Firmware > Upload

* Upload the openwrt-realtek-rtl838x-zyxel_gs1900-24-v1-initramfs-kernel.bin
  file by your preferred method to the previously determined partition.
  When prompted, select to boot from the newly flashed image, and reboot
  the switch.

* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:

  > sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24-v1-squashfs-sysupgrade.bin

U-Boot TFTP method:

* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).

* Set up a TFTP server on your client and make it serve the initramfs
  image.

* Connect serial, power up the switch, interrupt U-boot by hitting the
  space bar, and enable the network:

  > rtk network on

> Since the GS1900-24 v1 is a dual-partition device, you want to keep the
  OEM firmware on the backup partition for the time being. OpenWrt can
  only be installed in the first partition anyway (hardcoded in the
  DTS). To ensure we are set to boot from the first partition, issue the
  following commands:

  > setsys bootpartition 0
  > savesys

* Download the image onto the device and boot from it:

  > tftpboot 0x81f00000 192.168.1.10:openwrt-realtek-rtl838x-zyxel_gs1900-24-v1-initramfs-kernel.bin
  > bootm

* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:

  > sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24-v1-squashfs-sysupgrade.bin

Signed-off-by: Martin Kennedy <hurricos@gmail.com>
2022-03-13 19:24:13 +01:00
INAGAKI Hiroshi
7b19770525 realtek: add support for I-O DATA BSH-G24MB
I-O DATA BSH-G24MB is a 24 port gigabit switch, based on RTL8382M.

Specification:

- SoC		: Realtek RTL8382M
- RAM		: DDR2 128 MiB (Nanya NT5TU128M8HE-AC)
- Flash		: SPI-NOR 16 MiB (Macronix MX25L12835FM2I-10G)
- Ethernet	: 10/100/1000 Mbps x24
  - port 1-8	: RTL8218B
  - port 9-16	: RTL8218B (SoC)
  - port 17-24	: RTL8218B
- LEDs/Keys	: 2x, 1x
- UART		: pin header on PCB
  - JP2: 3.3V, TX, RX, GND from rear side
  - 115200n8
- Power		: 100 VAC, 50/60 Hz
  - Plug	: IEC 60320-C13

Flash instruction using sysupgrade image:

1. Boot BSH-G24MB normally
2. Connect BSH-G24MB to the DHCP enabled network
3. Find the device's IP address and open the WebUI and login
   Note: by default, the device obtains IP address from DHCP server of
         the network
4. Open firmware update page ("ファームウェア アップデート")
5. Rename the OpenWrt sysupgrade image to "bsh-g24mb_v100.image" and
   select it
6. Press apply ("適用") button to perform update
7. Wait ~150 seconds to complete flashing

Note:

- BSH-G24MB has a power-related LED ("電源"), but it's not connected to
  the GPIO of the SoC or RTL8231 and cannot be controlled. Instead of
  it, use system status LED on other than running-state.

- "sys_loop" LED indicates system status and loop-detection status in
  stock firmware.

- BSH-G24MB has 2x os-image partitions named as "RUNTIME"/"RUNTIME2" in
  16 MiB SPI-NOR flash and the size of image per partition is only
  6848 KiB. The secondary image is never used on stock firmware, so also
  use it on OpenWrt to get more space.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-03-07 21:44:53 +01:00
Bjørn Mork
0890fb2df4 realtek: net: dsa: configure better brport flags when ports leave the bridge
Ensures that the DSA driver sets exactly the same default flags as the
bridge when a port joins or leaves.  Without this we end up with a
confusing flag mismatch, where DSA and bridge ports use different sets
of flags.

This is critical as the "learning" mismatch will be harmful to the
network, causing all traffic to be flooded on all ports.

The original commit was buggy, trying to set the flags one-by-one in a
loop.  This was not supported by the API and the end result was that
all but the last flag were cleared.  This bug was implicitly fixed
upstream by commit e18f4c18ab5b ("net: switchdev: pass flags and mask
to both {PRE_,}BRIDGE_FLAGS attributes").

This is a minimum temporary stop measure fix for the critical lack of
"learning" only.  The major API change associated with a full v5.12+
backport is neither required nor wanted. A simpler fix, moving the
call to dsa_port_bridge_flags() out of the loop,  has therefore been
merged into this modified backport.

Fixes: afa3ab54c0 ("realtek: Backport bridge configuration for DSA")
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Acked-by: Daniel Golle <daniel@makrotopia.org>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
[fix typos in commit message]
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-03-06 22:01:04 +02:00
John Audia
0989b7ad3a kernel: bump 5.10 to 5.10.102
Removed upstreamed:
	bcm4908/patches-5.10/180-i2c-brcmstb-fix-support-for-DSL-and-CM-variants.patch[1]

All other patches automatically rebased.

1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.102&id=f333c1916fd6b55900029bf8f918cc00009e2111

Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200

Signed-off-by: John Audia <graysky@archlinux.us>
2022-03-01 21:38:36 +01:00
Sander Vanheule
66d8db01cc realtek: remove debugging code from timer
Remove some (dead) debugging code from the Realtek timer to clean up the
sources of this driver.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:58 +00:00
Sander Vanheule
9db651f4a2 realtek: use DT provided address for timers
The I/O base address for the timers was hardcoded into the driver,
or derived from the HW IRQ number as an even more horrible hack. All
supported SoC families have these timers, but with hardcoded addresses
the code cannot be reused right now.

Request the timer's base address from the DT specification, and store it
in a private struct for future reference.

Matching the second interrupt specifier, the address range for the
second timer is added to the DT specification.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:58 +00:00
Sander Vanheule
71810eb068 realtek: clean up RTL930x timer DT node
The Realtek timer node for RTL930x doesn't have any child nodes, making
the use of '#address-cells' quite pointless. It is also not an interrupt
controller, meaning it makes no sense to define '#interrupt-cells'.

The I/O address for this node is also wrong, but this is hidden by the
fact that the driver associated with this node bypasses the usual DT
machinery and does it's own thing. Correct the address to have a sane
value, even though it isn't actually used.

Fixes: a75b9e3ecb ("realtek: Adding RTL930X sub-target")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:58 +00:00
Sander Vanheule
fa20f2bfc7 realtek: ZyXEL GS1900-48: fix system LED polarity
When driven by a GPIO pin, the system LED needs to be configured as
active high. Otherwise the LED switches off after booting and
initialisation.

Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
66140820e1 realtek: ZyXEL GS1900-48: drop status from gpio1
The default value for a DT node's status property is already "okay", so
there's no need to specify it again. Drop the status property to clean
up the DTS.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
a39fbaf23a realtek: use higher priority for timer interrupts
The assigned output index for the event timers was quite low, lower even
than the ethernet interrupt. This means that high network load could
preempt timer interrupts, possibly leading to all sorts of strange
behaviour.

Increase the interrupt output index of the event timers to 5, which is
the highest priority output and corresponds to the (otherwise unused)
MIPS CPU timer interrupt.

Fixes: a75b9e3ecb ("realtek: Adding RTL930X sub-target")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
4b31717fb0 realtek: move RTL8231 definitions to board files
The RTL8231 is an external chip, and not part of the SoC. That means
it is more appropriate to define it in the board specific (base) files,
instead of the DT include for the SoC itself.

Moving the RTL8231 definition also ensures that boards with no GPIO
expander, or an alternative one, don't have a useless gpio1 node label
defined.

Tested on a Netgear GS110TPPv1.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
004d4d66c8 realtek: fix node addresses for RTL839x
The address in some node names doesn't match the actual offset specified
in the DT node. Update the names to fix this.

While fixing the node names, also drop the unused node labels.

Fixes: 0a7565e536 ("realtek: Update rtl839x.dtsi for realtek,rtl-intc, new gpio controller remove RTL8231 node")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
1ca081000a realtek: consolidate bootargs again
Bootargs for devices in the realtek target were previously consolidated
in commit af2cfbda2b ("realtek: Consolidate bootargs"), since all
devices currently use the same arguments.

Commit a75b9e3ecb ("realtek: Adding RTL930X sub-target") reverted this
without any argumentation, so let's undo that.

Commit 0b8dfe0851 ("realtek: Add RTL931X sub-target") introduced the
old bootargs also for RTL931x, without providing any actual device
support. Until that is done, let's assume vendors will have done what
they did before, and use a baud rate of 115200.

Fixes: a75b9e3ecb ("realtek: Adding RTL930X sub-target")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Birger Koblitz
4d8020072e realtek: fix locking bug in rtl838x_hw_receive()
A Locking bug in the packet receive path was introduced with PR
#4973. The following patch prevents the driver from locking
after a few minutes with an endless flow of

[ 1434.185085] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000f8
[ 1434.208971] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc
[ 1434.794800] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc
[ 1435.049187] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc

Signed-off-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
2022-02-18 12:35:03 +00:00
Sander Vanheule
a93dfff10e realtek: add RTL8231 chip detection
When initialising the driver, check if the RTL8231 chip is actually
present at the specified address. If the READY_CODE value does not match
the expected value, return -ENXIO to fail probing.

This should help users to figure out which address an RTL8231 is
configured to use, if measuring pull-up/-down resistors is not an
option.

On an unsuccesful probe, the driver will log:
    [    0.795364] Probing RTL8231 GPIOs
    [    0.798978] rtl8231_init called, MDIO bus ID: 30
    [    0.804194] rtl8231-gpio rtl8231-gpio: no device found at bus address 30

When a device is found, only the first two lines will be logged:
    [    0.453698] Probing RTL8231 GPIOs
    [    0.457312] rtl8231_init called, MDIO bus ID: 31

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-02-17 19:11:42 +02:00
Sander Vanheule
44f7cfd760 realtek: always require SMI bus ID for RTL8231
The SMI bus ID for RTL8231 currently defaults to 0, and can be
overridden from the devicetree. However, there is no value check on the
DT-provided value, aside from masking which would only cause value
wrap-around.

Change the driver to always require the "indirect-access-bus-id"
property, as there is no real reason to use 0 as default, and perform a
sanity check on the value when probing. This allows the other parts of
the driver to be simplified a bit.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-02-17 19:11:37 +02:00
Sander Vanheule
5da2e0cc20 realtek: use automatic GPIO numbering for RTL8231
Set the gpio_chip.base to -1 to use automatic GPIO line indexing.
Setting base to 0 or a positive number is deprecated and should not be
used.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-02-17 19:11:33 +02:00
Sander Vanheule
851212a714 realtek: fix RTL8231 gpio count
The RTL8231's gpio_chip.ngpio was set to 36, which is the largest valid
GPIO index. Fix the allowed number of GPIOs by setting ngpio to 37, the
actual line count.

Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-02-17 19:11:17 +02:00
Daniel Golle
eef7f17652 realtek: rtl83xx-phy: abstract and document PHY features
Replace magic values with more self-descriptive code now that I start
to understand more about the design of the PHY (and MDIO controller).

Remove one line before reading RTL8214FC internal PHY id which turned
out to be a no-op and can hence safely be removed (confirmed by
INAGAKI Hiroshi[1])

[1]: df8e6be59a (r66890713)

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:37:03 +00:00
Birger Koblitz
68c66b0fa3 realtek: fix locking issues
Fixe a coupld of locking issues found by applying lock
debugging to the code.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Daniel Golle
b53202a8c3 realtek: switch to use generic MDIO accessor functions
Instead of directly calling SoC-specific functions in order to access
(paged) MII registers or MMD registers, create infrastructure to allow
using the generic phy_*, phy_*_paged and phy_*_mmd functions.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:21:47 +00:00
Daniel Golle
af93bf6129 realtek: implement Clause-45 MDIO write on rtl931x
* Add missing Clause-45 write support for rtl931x
 * Switch to use helper functions in all Clause-45 access functions to
   make the code more readable.
 * More meaningful/unified debugging output (dynamic kprintf)

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:21:47 +00:00
Daniel Golle
854458f986 realtek: backport Clause-45 MDIO helper functions
Import commit ("c6af53f038aa3 net: mdio: add helpers to extract clause
45 regad and devad fields") from Linux 5.17 to allow making the MDIO
code in the ethernet driver more readable.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:21:47 +00:00
Birger Koblitz
0538dc693b realtek: add support for port led configuration on RTL93XX
Using the led-set attribute of a port in the dts we allow configuration
of the port leds. Each led-set is being defined in the led-set configuration
of the .dts, giving a specific configuration to steer the port LEDs via a serial
connection.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
caaac9ab3b realtek: Add support for the RTL8221B PHY
The RTL8221B PHY is a newer version of the RTL8226, also supporting
2.5GBit Ethernet. It is found with RTL931X devices such as the
EdgeCore ECS4125-10P

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
08cf48c344 realtek: Add specific PHY polling options to support the Zyxel XGS1250/XGS1210
Both the Aquantia AQR113c and the RTL8226 PHYs in the Zyxel XGS1250 and the
Zyxel XGS1210 require special polling configuration settings in the
RTL930X_SMI_10GPHY_POLLING_REGxx_CFG configuration registers. Set them.
Additionally, for RTL 1GBit phys set the RTL930X_SMI_PRVTE_POLLING_CTRL bits
in the poll mask.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
3cab11ad13 realtek: Fix link status detection on RTL9302 for SFP modules
For SFP slots on the RTL9302, the link status is not correctly detected.
Use the link media status instead.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
0b8dfe0851 realtek: Add RTL931X sub-target
We add the RTL931X sub-target with kernel configuration for
a dual core MIPS InterAptive CPU.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
9ed6097054 realtek: Add HW support for RTL931X for PIE, L2 and STP aging
We add HW support routines for the RTL931X SoC family for handling
the Packet Inspection Engine, L2 table handling and STP aging.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
724e4af530 realtek: Store and Restore MC memberships for port enable/disable
We need to store and restore MC memberships in HW when a port joins or
leaves a bridge as well as when it is enabled or disabled, as these
properties should not change in these situations.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
d22923be66 realtek: Copy all BPDUs to the kernel
In order to receive STP information at the kernel level, we make sure
that all Bridge Protocol Data Units are copied to the CPU-Port.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
9d396fc1e8 realtek: Add L2 aging configuration functions for all SoC families
Instead of a generic L2 aging configuration function with complex
logic, we implement an individual function for all SoC types.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
f3c5e7ddcc realted: Add DSA bridge offload configuration
Add functionality to enable or disable L2 learning offload and port flooding
for RTL83XX.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
afa3ab54c0 realtek: Backport bridge configuration for DSA
Adds the DSA API for bridge configuration (flooding, L2 learning,
and aging) offload as found in Linux 5.12 so that we can implement
it in our drivver.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
32e5b5ee6b realtek: Add Link Aggregation (aka trunking) support
This adds LAG support for all 4 SoC families, including support
ofr the use of different distribution algorithm for the load-
balancing between individual links.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
8557b458e2 realtek: Backport LAG functionality for DSA
Add the LAG configuration API for DSA as found in Linux 5.12 so that we
can implement it in the dsa driver.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
77f3e2ea17 realtek: Cleanup setting inner/outer PVID and Ingress/Egres VLAN filtering
Use setting functions instead of register numbers in order to clean up the code.
Also use enums to define inner/outer VLAN types and the filter type.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
5b8b382df9 realtek: Add support for ZxXEL XGS1250-12 Switch
The ZyXEL XGS1250-12 Switch is a 11 + 1 port multi-GBit switch with
8 x 1000BaseT, 3 x 1000/2500/5000/10000BaseT Ethernet ports and
1 SFP+ module slot.

Hardware:
 - RTL9302B SoC
 - Macronix MX25L12833F (16MB flash)
 - Nanja NT5CC64M16GP-1 (128MB DDR3 SDRAM)
 - RTL8231 GPIO extender to control the port LEDs
 - RTL8218D 8x Gigabit PHY
 - Aquantia AQR113c 1/2.5/5/10 Gigabit PHYs
 - SFP+ 10GBit slot

Power is supplied via a 12V 2A standard barrel connector. At the
right side behind the grid is UART serial connector. A Serial
header can be connected to from the outside of the switch trough
the airvents with a standard 2.54mm header.
Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial
connection is via 115200 baud, 8N1.

A reset button is accessble through a hole in the front panel

At the time of this commit, all ethernet ports work under OpenWRT,
including the various NBaseT modes, however the 10GBit SFP+ slot is not
supported.

Installation
--------------
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* Navigate to 'Management' in the OEM web interface and click on 'Firmware upgrade'
  to the left.
* Upload the OpenWrt initramfs image, and wait till the switch reboots.
* Connect to the device through serial and change the U-boot boot command.
  > fw_setenv bootcmd 'rtk network on; boota'
* Reboot, scp the sysupgrade image to /tmp, verify the checksum and flash it:
  > sysupgrade /tmp/openwrt-realtek-rtl930x-zyxel_xgs1250-12-squashfs-sysupgrade.bin
* Upon reboot, you have a functional OpenWrt installation. Leave the bootcmd
  value as is - without 'rtk network on' the switch will fail to initialise
  the network.

Web recovery
------------
The XGS1250-12 has a handy web recovery that will load when U-boot does
not find a bootable kernel. In case you would like to trigger the web
recovery manually, partially overwrite the firmware partition with some
zeroes:

  # dd if=/dev/zero of=/dev/mtd5 bs=1M count=2

If you have serial connected you'll see U-boot will start the web recovery
and print it's listening on 192.168.1.1, but by default it seems to be on
the OEM default IP for the switch - 192.168.1.3. The web recovery only
listens on HTTP (80) and *not* on 443 (HTTPS) unlike the web UI.

Return to stock
---------------
You can flash the ZyXEL firmware images to return to stock:

  # sysupgrade -F -n XGS1250-12_Firmware_V1.00(ABWE.1)C0.bix

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
400676e442 realtek: Add RTL930X sub-target
Adds the sub-target for the RTL930X-based routers. Adds an
initial kernel configuration.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
7026084066 realtek: Add SDS configuration routines for the RTL93XX platforms
Adds configuration routines for the internal SerDes of the
RTL930X and RTL931X.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
51c8f76612 realtek: Improve MAC config handling for all SoCs
Adds a rtl931x_phylink_mac_config for the RTL931X and improve
the handling of the RTL930X phylink configuration. Add separate
handling of the RTL839x since some configurations are different
from the RTL838X.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
c7cc4e95a5 realtek: Add support for detecting RTL9303 SoCs
Adds support for detecting RTL9303 SoCs as found e.g.
in the Ubiquiti USW switch.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
60df655d5b realtek: Allow PHY-IDs to differ from Port numbers
We were using the PHY-ids (the reg entries in the PHY
sections of the .dts) as the port numbers. Now scan the
ports section in the .dts, and use the actual port numbers,
following the phy-handle to the PHY properties.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
bf0ffe3310 realtek: Use SerDes Information from .dts for phylink config
When a port is brought up, read the SDS-id via the phy_device
for a given port and use this to configure the SDS when it
is brought up.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
8079574f2c realtek: Remove RTL838X PHY firmware from RTL839X kernel
The RTL839X does not have an internal phy and thus does not need to have any
firmware as part of the kernel, especially not firmware for the RTL838X.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
a825835942 realtek: Improve IRQ request in Ethernet driver
Improves the IRQ request code by using platform_get_irq() which provides
better error handling.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
a75b9e3ecb realtek: Adding RTL930X sub-target
This adds the RTL931X sub-target in the realtek target Makefile.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
5cb2828092 realtek: Use new CEVT timer
Selects the new CEVT timer for Realtek instead of the previous
timer driver. While we are at it, we explicitily state we do
not use the I2C driver of the RTL9300.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
775d903216 realtek: Replace the RTL9300 generic timer with a CEVT timer
The RTL9300 has a broken R4K MIPS timer interrupt, however, the
R4K clocksource works. We replace the RTL9300 timer with a
Clock Event Timer (CEVT), which is VSMP aware and can be instantiated
as part of brining a VSMTP cpu up instead of the R4K CEVT source.
For this we place the RTL9300 CEVT timer in arch/mips/kernel
together with other MIPS CEVT timers, initialize the SoC IRQs
from a modified smp-mt.c and instantiate each timer as part
of the MIPS time setup in arch/mips/include/asm/time.h instead
of the R4K CEVT, similarly as is done by other MIPS CEVT timers.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
0536c582e6 realtek: Fix RTL931X Ethernet driver
Various fixes to enable Ethernet on the RTL931X:
 - Network start and stop sequence for RTL931X HW
 - MDIO access on RTL931X SoC
 - Chip initialization
 - SerDes setup

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
1b1f05f682 realtek: Fix Ethernet driver IRQ service routine for SMP
Do not lock the register structure in IRQ context. It is not
necessary and leads to lockups under SMP load.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
9d847244d9 realtek: fix RTL839X receive tag decoding
Correct offset in RX tag structure. Correct offload decision flagging.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
6b79484268 realtek: Add SerDes access functions for RTL931X
Adds RTL931X SerDes access functions as needed by the Ethernet driver.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
6378d72ef6 realtek: Fix RTL931X-specific Ethernet driver functions
Fix the update counter of the RX ring, add SDS access functions
for RTL931X.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
9024202052 realtek: rename rtl838x_reg structure
Rename the SoC-specific rtl838x_reg structure in the Ethernet
driver to avoid confusion with the structure of the same name
in the DSA driver. New name is: rtl838x_eth_reg

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
2f51e567ff realtek: Fix RTL839x TX CPU-Tag
Setting bits 20 and 23 in a u16 is obviously wrong.
According to https://www.svanheule.net/realtek/cypress/cputag
cpu_tag[2] starts at bit 48 in the cpu-tag structure, so
bit 43 is bit 5 in cpu_tag[2] and bit 40 is bit 8 in
cpu_tag[2].

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
b3287a2165 realtek: Increase zone size for Ethernet driver DMA
Set CONFIG_FORCE_MAX_ZONEORDER setting to 13 to allow larger
contiguous memory allocation for the DMA of the Ethernet
driver. Increase the number of entries in the RX ring
to 300 making use of the larger DMA region now possible for
receiveing packets.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
47f5a0a3ee realtek: Add support for ZyXEL GS1900-48 Switch
The GS1900-48 is a 48 + 2 port Gigabit L2 switch with 48 gigabit ports.
Hardware:
    RTL8393M SoC
    Macronix MX25l12805D (16MB flash)
    128MB RAM
    6 * RTL8218B external PHY
    2 * RTL8231 GPIO extenders to control the port LEDs, system LED and
    Reset button

2 Uplink ports are SFP cages which support 1000 Base-X mini GBIC modules.

Power is supplied via a 230 volt mains connector.
The board has a hard reset switch SW1, which is is not reachable from the outside.
J4 provides a 12V RS232 serial connector which is connected through U8 to
the 3.3V UART of the RTL8393. Conversion is done by U8, a SIPEX 3232EC.
To connect to the UART, wires can be soldered to R603 (TX)  and R602 (RX).

Installation:
Install the squashfs image via Realtek's original Web-Interface.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
0a7565e536 realtek: Update rtl839x.dtsi for realtek,rtl-intc, new gpio controller remove RTL8231 node
Update the IRQ configuration to work with the new rtl-intc controller.
Also change all KSEG1 addresses in reg = <> of the devics to physical
addresses.

Use the new gpio-otto controller instead of the legacy driver.
Also remove the memory node as this is better put into a device .dts.

Also remove the RTL8231 GPIO controller node from this base file
since the chip might not be found in all Realtek RTL839x devices.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
1df2f8d831 realtek: Update RTL838X DTS to new Realtek IRQ controller notation
Replace the interrupt controller node with the new realtek,rtl-intc
node and change all device interrupts to use the 2 field notation:
interrupts = <[SoC IRQ] [Index to MIPS IRQ]>

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
6c18e9c491 realtek: Add VPE support for the IRQ driver
In order to support VSMP, enable support for both VPEs
of the RTL839X and RTL930X SoCs in the irq-realtek-rtl
driver. Add support for IRQ affinity setting.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
0c9f614c99 realtek: Add kernel config for RTL839x SoCs
Adds a dedicated kernel configuration for RTL839X SoCs
enabling SMP.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
04489b7255 realtek: Enable Multithreading support in prom.c
Adds Multithreading support functions in prom.c.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
f603090311 realtek: Change Platform defines to depend on CONFIG_RTL83XX
In order for the Platform includes to be available on
all sub-targets, make them dependent on CONFIG_RTL83XX.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
4021dd527b realtek: Optimize kernel configuration for RTL838X
The RTL838X SoCs do not use Aquantia PHYs, remove this.
Also the RTL838X uses a high resolution R4K timer.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
fce11f6849 realtek: Create 4 different Realtek Platforms
Creates RTL83XX as a basic kernel config parameter for the
RTL838X, RTL839x, RTL930X and RTL931X platforms with respective
configurations for the SoCs, which are introduced in addition.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
0d7cace7bd realtek: Create rtl838x sub-target specific makefiles
Create the RTL838x specific Makefiles. Move CPU-type into
rtl838x.mk as this is specifc to that platform. Add
rtl838x subtarget into main Makefile.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
47be1943ed realtek: Add initial kernel config for RTL838x sub-target
Move the generic kernel configs to the rtl838x sub-target.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:46 +00:00
Birger Koblitz
8de54c2ce6 realtek: Add Makefile for RTL839x sub-architecture
Adds the initial Makefile for the RTL839x sub-architecture.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:46 +00:00
Birger Koblitz
cf8e145955 realtek: Set RTL838X sub-target specific properties
This defines the sub-target specific properties for the RTL838X
sub-target.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:46 +00:00
Birger Koblitz
14705ae3bd realtek: Create rtl838x subtarget
mv generic/target.mk to rtl838x/target.mk in order to create
an initial makefile for the rtl838x sub-architecture

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:46 +00:00
Birger Koblitz
45053b507c realtek: Add support for SFP EEPROM-access over SMBus
The EEPROMs on SFP modules are compatible both to I2C as well
as SMBus. However, the kernel so far only supports I2C
access. We add SMBus access routines, because the I2C driver
for the RTL9300 HW only supports that protocol. At the same
time we disable I2C access to PHYs on SFP modules as otherwise
detection of any SFP module would fail. This is not in any
way problematic at this point in time since the RTL93XX
platform so far does not support PHYs on SFP modules.

The patches are copied and rebased version of:
https://bootlin.com/blog/sfp-modules-on-a-board-running-linux/

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:46 +00:00
Birger Koblitz
f4bdb7fdcc realtek: Add support for RTL9300/RTL9310 I2C multiplexing
The RTL9300/RTL9310 I2C controllers have support for 2 independent I2C
masters, each with a fixed SCL pin, that cannot be changed. Each of these
masters can use 8 (RTL9300) or 16 (RTL9310) different pins for SDA.
This multiplexer directly controls the two masters and their shared
IO configuration registers to allow multiplexing between any of these
busses. The two masters cannot be used in parallel as the multiplex
is protected by a standard multiplex lock.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:46 +00:00
Birger Koblitz
63a0a4d85b realtek: Add support for RTL9300/RTL9310 I2C controller
This adds support for the RTL9300 and RTL9310 I2C controller.
The controller implements the SMBus protocol for SMBus transfers
over an I2C bus. The driver supports selecting one of the 2 possible
SCL pins and any of the 8 possible SDA pins. Bus speeds of
100kHz (standard speed) and 400kHz (high speed I2C) are supported.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:46 +00:00
Birger Koblitz
48dd446614 realtek: remove legacy GPIO driver support
This patch removes support for the legacy GPIO driver, since now
the gpio-otto driver can be used on all platforms

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:46 +00:00
Birger Koblitz
2314ba725b realtek: Add GPIO support for RTL930X and RTL931X
We add support for the RTL930X and RTL931X architectures
in the gpio-realtek-otto.c driver.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:46 +00:00
Daniel Golle
58b82e6ca5 realtek: drop support for Linux 5.4
Drop patches and files for Linux 5.4 now that we've been using 5.10
for a while and support for Linux 5.4 has gone out-of-sync.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:21:46 +00:00
John Audia
c391dcdf86 kernel: bump 5.10 to 5.10.100
All patches automatically rebased.

Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200

Signed-off-by: John Audia <graysky@archlinux.us>
2022-02-11 23:17:40 +01:00
John Audia
5e43dd1fa7 kernel: bump 5.10 to 5.10.99
Had to update generic defconfig (make kernel_menuconfig CONFIG_TARGET=generic)
for this bump, but since that only modifies the target defined in .config,
and since that target also needed to be updated for unrelated reasons, manually
propagated the newly added symbol to the generic config.

Removed upstreamed:
    pending-5.10/860-Revert-ASoC-mediatek-Check-for-error-clk-pointer.patch[1]

All other patches automatically rebased.

1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.99&id=080f371d984e8039c66db87f3c54804b0d172329

Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200

Signed-off-by: John Audia <graysky@archlinux.us>
2022-02-11 23:17:40 +01:00
John Audia
7bf62e2451 kernel: bump 5.4 to 5.4.169
All patches automatically rebased.

Build system: x86_64
Build-tested: ramips/mt7621*

*Had to revert 7f1edbd in order to build due to FS#4149

Signed-off-by: John Audia <graysky@archlinux.us>
2022-01-03 01:00:03 +01:00
Sander Vanheule
ebc0ce118f realtek: netgear-gs110tpp: Add system LEDs
The GS110TPP has an RGB LED used for system status indication. Expose
all three components as separate GPIO LEDs connected via the device's
RTL8231.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2021-12-27 13:51:41 +01:00
Sander Vanheule
c88124cfc4 realtek: netgear-gigabit: Enable RTL8231
Since the move to 5.10, there are now two GPIO drivers. The gpio0 node
refers to the internal GPIOs, so the indirect-access-bus-id is no longer
relevant for that node.

Set indirect-access-bus-id to the correct value (31) on the correct node
(gpio1) and enable the device.

Cc: Raylynn Knight <rayknight@me.com>
Cc: Michael Mohr <akihana@gmail.com>
Cc: Stijn Segers <foss@volatilesystems.org>
Cc: Stijn Tintel <stijn@linux-ipv6.be>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Bjørn Mork <bjorn@mork.no>
2021-12-27 13:51:41 +01:00
Sergey Ryazanov
fa3690f8f1 kernel: 5.10: consolidate mac80211 crypto options
Each of
- CRYPTO_AEAD2
- CRYPTO_AEAD
- CRYPTO_GF128MUL
- CRYPTO_GHASH
- CRYPTO_HASH2
- CRYPTO_HASH
- CRYPTO_MANAGER2
- CRYPTO_MANAGER
- CRYPTO_NULL2

either directly required for mac80211 crypto support, or directly
selected by such options. Support for the mac80211 crypto was enabled in
the generic config since c7182123b9 ("kernel: make cryptoapi support
needed by mac80211 built-in"). So move the above options from the target
configs to the generic config to make it clear why do we need them.

CC: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
2021-12-17 16:16:34 +01:00
Sergey Ryazanov
b61ab8f57e kernel: filter out both Clang and LLD versions
Both CLANG_VERSION and LLD_VERISON are autogenerated runtime
configuration options, so add them to the kernel configuration filter
and remove from generic and per-target configs to keep configs clean.

Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
2021-12-17 16:16:34 +01:00
John Audia
43c0a12665 kernel: bump 5.10 to 5.10.85
Removed target for patch which does not exist:
    bcm27xx/patches-5.10/950-0249-kbuild-Disable-gcc-plugins.patch

All patches automatically rebased.

Build system: x86_64
Build-tested: bcm2711/RPi4B, ipq806x/R7800*
Run-tested: bcm2711/RPi4B, ipq806x/R7800*

* Had to revert 7f1edbd412 in order to build
  (binutils 2.37, https://bugs.openwrt.org/index.php?do=details&task_id=4149)

Signed-off-by: John Audia <graysky@archlinux.us>
2021-12-17 15:10:22 +01:00
John Audia
6c945fa379 kernel: bump 5.10 to 5.10.83
Removed upstreamed:
    bcm53xx/patches-5.10/033-v5.16-0024-ARM-dts-BCM5301X-Fix-I2C-controller-interrupt.patch[1]
    bcm53xx/patches-5.10/033-v5.16-0025-ARM-dts-BCM5301X-Add-interrupt-properties-to-GPIO-no.patch[2]

All other patches automatically rebased.

1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.83&id=b2cd6fdcbe0a5cb44e4610a08cc58261d494a885
2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.83&id=9db1d4a3c2700e1cc84c3d61199411d75c2a3ec6

Build system: x86_64*
Build-tested: bcm2711/RPi4B, ipq806x/R7800†
Run-tested: bcm2711/RPi4B, ipq806x/R7800†

* Had to revert 7c99085bd6 in order to build
  (latest bump of ca-certificates)

† Had to revert 7f1edbd412 in order to build
  (binutils 2.37, https://bugs.openwrt.org/index.php?do=details&task_id=4149)

Signed-off-by: John Audia <graysky@archlinux.us>
2021-12-12 21:11:30 +01:00
Bjørn Mork
afeda4a3d3 realtek: sort the port list numerically
Mac adresses are assigned in the order given by the port list.  The
interfaces are also brought up in this order.  This target supports
devices with up to 52 ports.  Sorting these alphabetically is very
confusing, and assigning mac addresses in alphabetic order does not
match stock firmware behaviour.

Suggested-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
2021-12-05 18:49:14 +01:00
Sander Vanheule
4304799b4a realtek: update watchdog timer patch
The Realtek Otto watchdog timer driver was accepted upstream, and is
queued for 5.17. Update the patch's file name, and replace by the final
version.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2021-12-05 18:49:14 +01:00
Sander Vanheule
22f85d63cf realtek: netgear-gigabit: Add gpio-restart node
The Netgear GS110TPP v1 switch cannot reliably perform cold reboots
using the system's internal reset controller.

On this device, and the other supported Netgear switches, internal GPIO
line 13 is connected to the system's hard reset logic. Expose this GPIO
on all systems to ensure restarts work properly.

Cc: Raylynn Knight <rayknight@me.com>
Cc: Michael Mohr <akihana@gmail.com>
Cc: Stijn Segers <foss@volatilesystems.org>
Cc: Stijn Tintel <stijn@linux-ipv6.be>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Bjørn Mork <bjorn@mork.no>
2021-11-28 22:43:08 +01:00
Sander Vanheule
3f4d6da453 realtek: Enable gpio-restart driver
Add the gpio-restart driver to the realtek build. This way devices,
which cannot reliably perform resets using the SoC's internal reset
logic, can use a GPIO line to drive the SoC's hard reset input.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2021-11-28 22:43:08 +01:00
Sander Vanheule
fa71139776 realtek: add missing GPIO irq properties
The internal GPIO controller on RTL838x is also an IRQ controller, which
requires the 'interrupt-controller' and '#interrupts-cells' properties
to be present in the device tree.

Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2021-11-28 22:43:08 +01:00
Bjørn Mork
d1464afe1b realtek: use full range of assigned MAC addresses
Some devices are assigned globally unique MAC addresses for all
ports. These are stored by U-Boot in the second U-Boot enviroment
("sysinfo") as a range of start and end address.

Use the full range if provided.

Signed-off-by: Bjørn Mork <bjorn@mork.no>
2021-11-28 22:43:08 +01:00
Bjørn Mork
9e7149f729 realtek: revert to "standard" management configuration
The default management interface should be easy to find for users
doing "blind" installations without console access.  There are
already multiple examples in the forum of advanced early adopters
having problems locating the management interface after installing
OpenWrt.

Requiring tagged VLAN configration to access the initial management
interface creates unnecessary hassle at best. Errors on the other
end are close to impossible to debug without console access, even
for advanced users.  Less advanced users might have problems with
the concept of VLAN tagging.

Limiting management access to a single arbitrary port among up to
52 possible LAN ports makes this even more difficult, for no
reason at all. Users might have reasons to use a different port
for management.  And they might even have difficulties using the
OpenWrt selected one. The port might be the wrong type for their
management link (e.g copper instead of fibre).  Or they might
depend on PoE power from a device which they can't reconfigure.

User expectations will be based on
- OpenWrt defaults for other devices
- stock firmware default for the device in question
- common default behaviour of similar devices

All 3 cases point to a static IP address accessible on the native
VLAN of any LAN port.  A switch does not have any WAN port.  All
ports are LAN ports.

This changes the default network configuration in line with these
expectations.

Cc: John Crispin <john@phrozen.org>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
2021-11-28 22:33:57 +01:00
John Audia
81995a5e77 kernel: bump 5.4 to 5.4.162
All patches automatically rebased.

Build system: x86_64
Build-tested: ramips/mt7621*

*I am hit with the binutils 2.37 bug so I had to revert 7f1edbd412
in order to downgrade to 2.35.1

Signed-off-by: John Audia <graysky@archlinux.us>
2021-11-28 16:32:45 +01:00
John Audia
bbdc13b15b kernel: bump 5.4 to 5.4.161
Removed upstreamed:
    ath79/patches-5.4/921-serial-core-add-support-for-boot-console-with-arbitr.patch[1]

Manually rebased:
    layerscape/patches-5.4/804-crypto-0016-MLKU-114-1-crypto-caam-reduce-page-0-regs-access-to-.patch
    octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch

All other patches automatically rebased.

1. Private email exchange with patch author, Hauke Mehrtens

Signed-off-by: John Audia <graysky@archlinux.us>
2021-11-28 16:32:45 +01:00
John Audia
894f483d20 kernel: bump 5.10 to 5.10.82
Removed upstreamed:
    bcm53xx/patches-5.10/033-v5.16-0014-ARM-dts-NSP-Fix-mpcore-mmc-node-names.patch

Manually rebased:
    ipq806x/patches-5.10/086-ipq8064-fix-duplicate-node.patch

All other patches automatically rebased.

Build system: x86_64
Build-tested: bcm2711/RPi4B, ipq806x/R7800
Run-tested: bcm2711/RPi4B, ipq806x/R7800

Signed-off-by: John Audia <graysky@archlinux.us>
2021-11-27 19:19:30 +01:00
Sander Vanheule
f8b2bc550b realtek: Remove _machine_restart and _machine_halt
By dropping _machine_restart, users can provide more reliable or
device-specific restart modes.

_machine_halt was already removed in commit f4b687d1f0 ("realtek: use
kernel defined halt"), but quietly reintroduced in commit 8faffa00cb
("realtek: add support for the RTL9300 timer"). Let's remove it again.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2021-11-24 21:43:56 +02:00
Sander Vanheule
927570f0a3 realtek: Add and enable watchdog node
Add and enable the Realtek Otto WDT peripheral found on these SoCs.

Default all devices to use standard (cold) reboot and "soc" resets.

Devices that require the PLL value fixup before restarting, should pick
the "cpu" or "software" reset mode. These devices also need to provide a
custom reboot mode, by adding the reboot argument to the kernel command
line:

    WDT reset mode  | kernel reboot mode
    ----------------+---------------------------------------
    soc             | reboot=cold (default if not specified)
    cpu             | reboot=warm
    software        | reboot=software

Preferrably, these devices should use an alternative restart method like
gpio-restart to provide reliable restarts.

Note that watchdog restarts are not yet exposed, since the
_machine_restart override is still present.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2021-11-24 21:43:42 +02:00
Sander Vanheule
b8fc5eecdc realtek: Backport Realtek Otto WDT driver
Add patch submitted upstream to linux-watchdog and replace the MIPS
architecture symbols. Requires one extra patch for the DIV_ROUND_*
macros, which have moved to a different header since 5.10.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2021-11-24 21:43:21 +02:00
Sander Vanheule
d3a62bea08 realtek: Add Lexra bus clock
The CPU peripherals on RTL83xx/RTL930x are connected to the CPU via the
Lexra bus. This bus can provide a clock signal to these peripherals, but
no clock driver is currently available. Instead, use a fixed-clock to
provide the clock frequency, and update the dependent peripherals.

Lexra bus clock frequencies:
- RTL838x: 200MHz
- RTL839x: 200MHz
- RTL930x: 175MHz

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2021-11-24 21:42:56 +02:00
Sander Vanheule
af2cfbda2b realtek: Consolidate bootargs
All current devices use identical bootargs, so let's move that to the
common devicetree includes.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2021-11-24 21:42:44 +02:00
Sander Vanheule
72ae8314f5 realtek: reset both ethernet NIC and queues
Recent versions of Realtek's SDK reset both the ethernet NIC and queues
(SW_NIC_RST and SW_Q_RST bits) when initialising the hardware.

Furthermore, when issuing a CPU reset on the Zyxel GS1900-8 (not
supported by any current driver), the networking part of the SoC is not
reset. This leads to unresponsive network after the restart. By
resetting both the ethernet NIC and queues, networking always comes up
reliably.

Suggested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2021-11-24 21:38:43 +02:00
Rui Salvaterra
3ae5da5adc kernel: bump 5.10 to 5.10.80
Deleted (upstreamed):
ath79/patches-5.10/921-serial-core-add-support-for-boot-console-with-arbitr.patch [1]
bcm53xx/patches-5.10/033-v5.15-0012-ARM-dts-BCM5301X-Fix-memory-nodes-names.patch [2]
lantiq/patches-5.10/0016-mtd-rawnand-xway-Keep-the-driver-compatible-with-on-.patch [3]
lantiq/patches-5.10/0110-MIPS-lantiq-dma-add-small-delay-after-reset.patch [4]
lantiq/patches-5.10/0111-MIPS-lantiq-dma-reset-correct-number-of-channel.patch [5]
lantiq/patches-5.10/0112-MIPS-lantiq-dma-fix-burst-length-for-DEU.patch [6]

Manually rebased:
ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch

[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.80&id=47462c5e600fbaffd755cd13dedd80d04e41ff83
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.80&id=2fde76df1885a6bec04317e457121326070450eb
[3] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.80&id=9b366f5221d8aa64b22f35be137a5749326444ce
[4] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.80&id=5af57ce8a6155fe3e4270d28d171abf8903bebc0
[5] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.80&id=b92a5df2c7adc79a57481445f67de0c1c716581f
[6] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.80&id=6b72caabc47011d03f44064452b2c65e8ed18326

Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
2021-11-19 09:40:29 +00:00
Sander Vanheule
c735d2e218 realtek: backport GPIO IRQ index fix
Backport the patch queued upstream for 5.16. The patch differs slightly
from the upstream patch due to an upstream change that added a
convenience function.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2021-11-01 00:56:51 +01:00
Rui Salvaterra
02026d0a6f kernel: bump 5.10 to 5.10.76
Deleted (upstreamed):
bcm27xx/patches-5.10/950-0145-xhci-add-quirk-for-host-controllers-that-don-t-updat.patch [1]

Manually rebased:
bcm27xx/patches-5.10/950-0355-xhci-quirks-add-link-TRB-quirk-for-VL805.patch
bcm53xx/patches-5.10/180-usb-xhci-add-support-for-performing-fake-doorbell.patch

Note: although automatically rebaseable, the last patch has been edited to avoid
conflicting bit definitions.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.10.y&id=b6f32897af190d4716412e156ee0abcc16e4f1e5

Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
2021-10-30 21:17:20 +02:00
Bjørn Mork
d990f805c0 realtek: re-enable IPv6 routing
Commit 03e1d93e07 ("realtek: add driver support for routing
offload") added routing offload for IPv4, but broke IPv6 routing
completely.  The routing table is empty and cannot be updated:

 root@gs1900-10hp:~# ip -6 route
 root@gs1900-10hp:~# ip -6 route add unreachable default
 RTNETLINK answers: Invalid argument

As a side effect, this breaks opkg on IPv4 only systems too,
since uclient-fetch fails when there are no IPv6 routes:

 root@gs1900-10hp:~# uclient-fetch http://192.168.99.1
 Downloading 'http://192.168.99.1'
 Failed to send request: Operation not permitted

Fix by returning NOTIFY_DONE when offloading is unsupported, falling
back to default behaviour.

Fixes: 03e1d93e07 ("realtek: add driver support for routing offload")
Signed-off-by: Bjørn Mork <bjorn@mork.no>
2021-10-30 15:00:22 +02:00
Bjørn Mork
daefc646e6 realtek: fix ZyXEL initramfs image generation
The current rule produces empty trailers, causing the OEM firmware
update application to reject our images.

The double expansion of a makefile variable does not work inside
shell code.  The second round is interpreted as a shell expansion,
attempting to run the command ZYXEL_VERS instead of expanding the
$(ZYXEL_VERS) makefile variable.

Fix by removing one level of variable indirection.

Fixes: c6c8d597e1 ("realtek: Add generic zyxel_gs1900 image definition")
Tested-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
2021-10-30 15:00:22 +02:00
Rui Salvaterra
d4f0e45f90 kernel: bump 5.10 to 5.10.75
Deleted (upstreamed):
bcm27xx/patches-5.10/950-0735-xhci-guard-accesses-to-ep_state-in-xhci_endpoint_res.patch [1]

[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.10.y&id=dc3e0a20dbb9dbaa22f4a33dea34230f8c663c40

Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
2021-10-21 00:17:36 +02:00
Rui Salvaterra
72e53eb133 kernel: bump 5.10 to 5.10.74
Patches automatically refreshed.

Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
2021-10-21 00:17:36 +02:00
John Audia
0ea33e5363 kernel: bump 5.4 to 5.4.155
All patches automatically rebased.

Signed-off-by: John Audia <graysky@archlinux.us>
2021-10-21 00:17:36 +02:00
John Audia
3d0499bcdb kernel: bump 5.4 to 5.4.154
All patches automatically rebased.

Signed-off-by: John Audia <graysky@archlinux.us>
2021-10-21 00:17:36 +02:00
Adrian Schmutzler
352427ecec realtek: switch to kernel 5.10
The usual testers did their tests. Now we need testers who use the
master builds.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-10-20 23:27:52 +02:00
John Audia
e672d1b387 kernel: bump 5.10 to 5.10.72
All patches automatically rebased.

Build system: x86_64
Build-tested: bcm2711/RPi4B
Run-tested: bcm2711/RPi4B

Signed-off-by: John Audia <graysky@archlinux.us>
2021-10-10 00:09:22 +01:00
Birger Koblitz
cda0460ad3 realtek: add legacy realtek GPIO driver for rtl9300 support
The otto GPIO driver does not work with rtl9300 SoCs. Add
the legacy driver again and use that by default in the 9300 .dtsi

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:06 +02:00
Birger Koblitz
4c83dae801 realtek: enable Aquantia PHY support
Enables Aquantia PHY support in the kernel

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:06 +02:00
Birger Koblitz
76f60470a1 realtek: Fix bug when accessing external PHYs on SoCs older than Revision C
RTL8393 SoCs older than Revision C hang on accesses to PHYs with PHY address
larger or equal to the CPU-port (52). This will make scanning the MDIO bus
hang forever. Since the RTL8390 platform does not support more than
52 PHYs, return -EIO for phy addresses >= 52. Note that the RTL8390 family
of SoCs has a fixed mapping between port number and PHY-address.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:06 +02:00
Birger Koblitz
88936e7e82 realtek: cleanup PHY driver
Removes unnecessary output from the RTL PHY drivers.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:06 +02:00
Birger Koblitz
1cfd45ae0b realtek: Add debugfs support for RTL9300
Adds support for debugfs on RTL9300, in particular the drop counters.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:06 +02:00
Birger Koblitz
1f402512ae realtek: Add SoC-specific routing offload implementation
Adds SoC specific routing offload implementations for
RTL8380/90 and RTL9300. RTL83xx supports merely nexthop
routing, RTL9300 full host and prefix routes.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:06 +02:00
Birger Koblitz
03e1d93e07 realtek: add driver support for routing offload
Add generic support for listening to FIB and Event notifier updates and
use this information to hook into the L3 hardware capabilities of the
RTL SoCs.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:06 +02:00
Birger Koblitz
ee6f483a62 realtek: Improve MDIO bus probing for RTL9300
Improve handling of multi-gig ports on the RTL9300 when probing
the MDIO bus.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:06 +02:00
Birger Koblitz
9ae927febd realtek: Fix bug in VLAN ingress and egress filtering
The ingress filter registers use 2 bits for each port to define the filtering
state, whereas the egress filter uses 1 bit. So for for the ingress filter
the register offset for a given port is:
(port >> 4) << 4: since there are 16 entries in a register of 32 bits
and for the egress filter:
(port >> 5) << 4: since there are 32 entries in a register of 32 bits

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:06 +02:00
Birger Koblitz
28e972b2ea realtek: Configure initial L2 learning setup
Configure a sane L2 learning configuration upon DSA driver load so that the
switch can start learning L2 addresses. Also configure the correct flood masks
for broadcast and unknown unicast traffice.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:06 +02:00
Birger Koblitz
9d9bf16aa8 realtek: Add phylink configuration routines for RTL93xx
This adds RTL93xx-specific MAC configuration routines that allow also configuration
of 10GBit links for phylink. There is support for the Realtek-specific HISGMI
protocol.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:06 +02:00
Birger Koblitz
a96b73a890 realtek: Packet Inspection Engine support for RTL930x SoCs
Adds the RTL930x-specific PIE support routines.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:05 +02:00
Birger Koblitz
2d8d81fe28 realtek: Packet Inspection Engine support for RTL839x SoCs
Adds the RTL839x-specific PIE support routines.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:05 +02:00
Birger Koblitz
87b3bd07a4 realtek: Packet Inspection Engine support for RTL838x SoCs
Adds the RTL838x-specific PIE support routines.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:05 +02:00
Birger Koblitz
54805fc911 realtek: Add driver support for TC offloading
This adds support for offloading TC flower by using the Packet Inspection Engine
of the RTL-SoCs. Basic infrastructure support is provide with callbacks to the
tc subsystem and support for HW packet counters.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:05 +02:00
Birger Koblitz
a6678accbd realtek: Add port to smi-bus address mapping
All RTL SoCs addresss PHYs via their port number, which is mapped to an
SMI address. Add support for configuring this mapping via the .dts on all
SoCs apart from the 839x, where the mapping to the 64 ports is fixed.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:05 +02:00
Birger Koblitz
2ab4d40293 realtek: Increase maximum RX ring buffer length
Increase the maximum ring buffer length in order to improve
performance on RTL839x devices.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:05 +02:00
Birger Koblitz
9eab76c84e realtek: Improve TX CPU-Tag usage
On RTL83xx enable learning of the MAC source address of the CPU port
from outgoing packets. Add documentation on bit fields. On RTL93xx
enable port-mask usage and the use of internal priority, these
SoCs automatically learn the MAC.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:05 +02:00
Birger Koblitz
ca04e2dfd0 realtek: Remove storm control and attack warnings
Remove the storm control and attack warnings from the IRQ handler
of the Ethernet driver. There was no consequence to the detection
and the kernel can also handle at least the attacks itself.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:05 +02:00
Birger Koblitz
e88ac0bbd1 realtek: Correct TX ring size in ethernet driver
This enlarges the size of the TX ring buffer, which prevents warnings
when the buffer runs out of space.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2021-10-09 08:25:05 +02:00
Paul Fertser
3810e89729 realtek: ensure output drivers are enabled in RTL8231
The bootloader can leave the GPIO expander in a state which doesn't have
output drivers enabled so GPIOs will properly work for input but output
operations will have no effect.

To avoid disrupting the boot in case the bootloader left direction and
data registers in an inconsistent state (e.g. pulling SoC's reset to 0)
reconfigure everything as input.

Reviewed-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
2021-10-02 21:26:12 +02:00
Rui Salvaterra
b4cee3b63f kernel: bump 5.10 to 5.10.70
Deleted (upstreamed):
bcm53xx/patches-5.10/181-Revert-USB-bcma-Add-a-check-for-devm_gpiod_get.patch

Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
2021-09-30 22:29:33 +01:00
Rui Salvaterra
2bf320a5e5 kernel: bump 5.10 to 5.10.69
Patches automatically refreshed.

Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
2021-09-30 22:29:33 +01:00
INAGAKI Hiroshi
fc050c7b53 realtek: add Kernel 5.10 as testing version
This patch adds "KERNEL_TESTING_PATCHVER:=5.10" to the Makefile in
realtek target to allow using Kernel 5.10 for testing.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:18 +02:00
INAGAKI Hiroshi
216011e424 realtek: enable uart1 on the devices with PoE support in 5.10
On the devices with PoE support, the secondary UART (uart1) on the SoC
is used to communicate between the SoC and controller.

Enable the secondary UART on the following devices:

- D-Link DGS-1210-10P
- Netgear GS110TPP v1
- Netgear GS310TP v1
- ZyXEL GS1900-8HP v1/v2
- ZyXEL GS1900-10HP
- ZyXEL GS1900-24HP v2

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:18 +02:00
INAGAKI Hiroshi
45b2a5d840 realtek: use physical addresses in soc dtsi in 5.10
Use physical addresses instead of virtual address in dts files.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:18 +02:00
INAGAKI Hiroshi
d7b349db7c realtek: use gpio-keys instead of "-polled" if SoC GPIO is used in 5.10
The new backported GPIO driver supports interrupt, so use gpio-keys
instead of gpio-keys-polled for keys connected to the internal GPIO
controller.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:18 +02:00
INAGAKI Hiroshi
61a3d0075b realtek: update GPIO bindings in the dts files in dts-5.10
this patch includes the following changes:

- adjust mapping for the new driver
  - GPIO 24 -> GPIO 0
  - GPIO 47 -> GPIO 0 (+ disabling system LED)

- disable pins in the invalid range
  (out of the range 0-31 of the new driver)
  - are these pins on the external RTL8231 (&gpio1)?
    - GPIO 67 (-> GPIO 3 on &gpio1?)
    - GPIO 94 (-> GPIO 30 on &gpio1?)

- drop "indirect-access-bus-id" property from gpio0 node in device dts
  files

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:18 +02:00
INAGAKI Hiroshi
2e676c05dc realtek: fix kernel panic in DSA driver for 5.10
dsa_to_port function in 5.10 returns dsa_port from the port list in
dsa_switch_tree, but the tree is built when the switch is registered
by dsa_register_switch and it's null in rtl83xx_mdio_probe.

So, we need to use dsa_to_port after the registration of the switch.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:18 +02:00
INAGAKI Hiroshi
99a658cb71 realtek: add pinmux node of LED_GLB_CTRL to rtl838x.dtsi in dts-5.10
This patch adds a pinctrl-single pinmux node to allow disabling system
LED and enabling GPIO 0 (old driver: GPIO 24).

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:18 +02:00
INAGAKI Hiroshi
a22602728c realtek: fix compile errors in dsa driver for 5.10
this patch fixes the following errors when compiling:

- dsa_switch_alloc is removed[1]

- a parameter "enum dsa_tag_protocol mprot" is added to dsa_tag_protocol
  in dsa_switch_ops (include/net/dsa.h)

- several paramters are added to "phylink_mac_link_up" in dsa_switch_ops
  (include/net/dsa.h)

  added:
    - int speed
    - int duplex
    - bool tx_pause
    - bool rx_pause

- a parameter "struct switchdev_trans *trans" is added to
  port_vlan_filtering in dsa_switch_ops (include/net/dsa.h)

[1]: https://lore.kernel.org/lkml/20191020031941.3805884-17-vivien.didelot@gmail.com/

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:18 +02:00
INAGAKI Hiroshi
9a4b8d6c30 realtek: fix compile errors in rtl838x_eth.c for 5.10
this patch fixes the following errors when compiling:

- "unsigned int txqueue" is added as an additional parameter of
  ndo_tx_timeout in net_device_ops (include/linux/netdevice.h)

- "mac_link_state" in phylink_mac_ops (include/linux/phylink.h)
  is renamed to "mac_pcs_get_state" and changed the return value
  to void from int

- several parameters are added to "mac_link_up" in phylink_mac_ops
  (include/linux/phylink.h) and the order of the parameters is
  changed

  added:
    - int speed
    - int duplex
    - bool tx_pause
    - bool rx_pause

- a parameter "phy_interface_t *interface" is added to of_get_phy_mode
  (drivers/of/of_net.c) and returns the state instead of phy mode

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:18 +02:00
INAGAKI Hiroshi
3069fffe60 realtek: add "soc" node to soc dtsi in dts-5.10
Add a "soc" node as a simple-bus to rtl838x.dtsi and rtl930x.dtsi.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
ddaeb73de0 realtek: update soc dtsi in 5.10 for backported drivers
this patch updates SoC dtsi (rtl838x.dtsi, rtl930x.dtsi) for the
following backported drivers:

- gpio-realtek-otto (5.13)
- spi-realtek-rtl (5.12)
- irq-realtek-rtl (5.12)

And, disable SoC GPIO node (gpio0) in rtl930x.dtsi in dts-5.10.
Currently, the upstreamed driver doesn't support the GPIO controller on
RTL930x SoC.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
1c020f8b43 realtek: cleanup and update soc dtsi in 5.10
the following changes are included in this patch:

- node is enabled by default, drop 'status = "okay"'
- adjust order of "compatible" lines and "reg" lines
- add a new blank line before fixed-link node in rtl830x.dtsi

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
0de230bd0c realtek: copy dts directory for Kernel 5.10
This patch adds "dts-5.10" directory to use backported drivers.
There are several specification changes in the new drivers, so there
are some compatibility issues in using dts/dtsi files for 5.4.

The old DTS files are moved to "dts-5.4", so their corresponding
kernel version is obvious as well.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[change "dts" to "dts-5.4", adjust Makefile]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
9e418b061c realtek: refresh and update config-5.10
This patch adjusts config-5.10 by running kernel_menuconfig.

Note:

- disable psb6970 phy driver (unused in realtek target?)

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
95f089dafe realtek: refresh patches for Kernel 5.10
This patch refresh all patches in patches-5.10/ to adjust for Kernel
5.10.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
46945e02d3 realtek: remove unnecessary line from rtl838x/Platform in 5.10
The following line is already defined in arch/mips/Kbuild.platforms by
300-mips-add-rtl838x-platform.patch.

platform-$(CONFIG_RTL838X) += rtl838x/

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
781f50705c realtek: drop fixup_bigphys_addr from ioremap.h in 5.10
A macro with the same name is provided in asm/pgtable.h in Kernel 5.10,
use it and drop from ioremap.h.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
2ec38bfea1 realtek: fix "help" line in Kconfig in files/patches for 5.10
In Kernel 5.10, "help" must be used instead of "---help---".

this patch fixes the following errors:

drivers/net/dsa/rtl83xx/Kconfig:7: syntax errorgit
drivers/net/dsa/rtl83xx/Kconfig:6: unknown statement "---help---"
drivers/net/dsa/rtl83xx/Kconfig:7:warning: ignoring unsupported character '.'
drivers/net/dsa/rtl83xx/Kconfig:7: unknown statement "This"
drivers/net/ethernet/Kconfig:170: syntax error
drivers/net/ethernet/Kconfig:169: unknown statement "---help---"
drivers/net/ethernet/Kconfig:170:warning: ignoring unsupported character '.'
drivers/net/ethernet/Kconfig:170: unknown statement "Say"
drivers/net/phy/Kconfig:331: syntax error
drivers/net/phy/Kconfig:330: unknown statement "---help---"
drivers/net/phy/Kconfig:331: unknown statement "Supports"

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
2cd00b5147 realtek: backport irq-realtek-rtl driver from 5.12 to 5.10
This patch backports "irq-realtek-rtl" driver to Kernel 5.10 from 5.12.
"MACH_REALTEK_RTL" is used as a platform name in upstream, but "RTL838X"
is used in OpenWrt, so update the dependency by the additional patch.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
b2bd0199a8 realtek: drop platform irq driver from 5.10
To use backported irq driver, drop old irq driver from realtek target
and call irqchip_init() in setup.c.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
9bac1c20b8 realtek: backport gpio-realtek-otto driver from 5.13 to 5.10
This patch backports "gpio-realtek-otto" driver to Kernel 5.10.
"MACH_REALTEK_RTL" is used as a platform name in upstream, but "RTL838X"
is used in OpenWrt, so update the dependency by the additional patch.

Note: GPIO mapping is changed in the upstreamed driver.

  old - new

   24 -  0
   25 -  1
   26 -  2
   27 -  3
   28 -  4
   29 -  5
   30 -  6
   31 -  7
   16 -  8
   17 -  9
   18 - 10
   19 - 11
   20 - 12
   21 - 13
   22 - 14
   23 - 15
    8 - 16
    9 - 17
   10 - 18
   11 - 19
   12 - 20
   13 - 21
   14 - 22
   15 - 23

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
fbd675c668 realtek: drop rtl838x gpio driver from 5.10
To backport the upstreamed driver (gpio-realtek-otto) from 5.13, drop the
old driver from realtek target.

And, modify 301-gpio-add-rtl838x-driver.patch to remove rtl838x GPIO
support and rename it only for rtl8231 GPIO support.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
0b000cbfe0 realtek: backport spi-realtek-rtl driver from 5.12 to 5.10
This patch backports "spi-realtek-rtl" driver to Kernel 5.10 from 5.12.
"MACH_REALTEK_RTL" is used as a platform name in upstream, but "RTL838X"
is used in OpenWrt, so update the dependency by the additional patch.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
1651bd9bc6 realtek: drop rtl838x spi-nor driver from 5.10
To backport the upstreamed driver (spi-realtek-rtl) from 5.12, drop the
old driver from realtek target.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2021-09-26 00:32:17 +02:00
INAGAKI Hiroshi
95170b4350 realtek: copy config/files/patches to 5.10
this patch copies the following files from 5.4 to 5.10:

- config-5.4   -> config-5.10
- files-5.4/   -> files-5.10/
- patches-5.4/ -> patches-5.10/

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[rebase on change in files-5.4]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-09-26 00:32:17 +02:00
Paul Fertser
16ae56b4f9 realtek: fix RTL8231 gpio expander for high GPIOs
GPIOs > 31 require special handling. This patch fixes both the
initialisation and direction get/set operations.

Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Sander Vanheule <sander@svanheule.net>
2021-09-25 19:28:54 +02:00