openofdm/verilog/coregen
2020-09-02 16:49:59 +02:00
..
div_gen_new_ip_core_zynq change the latency of divider from automatic 60 clocks to the original 36 clock 2020-09-02 16:49:59 +02:00
div_gen_new_ip_core_zynquplus change the latency of divider from automatic 60 clocks to the original 36 clock 2020-09-02 16:49:59 +02:00
div_gen_new_src extend support to zcu102/Zynq MPSoC ultra_scale 2020-04-27 15:46:16 +02:00
atan_lut_flist.txt add coregen files 2017-04-14 16:29:33 -04:00
atan_lut_xmdf.tcl add coregen files 2017-04-14 16:29:33 -04:00
atan_lut.asy add coregen files 2017-04-14 16:29:33 -04:00
atan_lut.gise add coregen files 2017-04-14 16:29:33 -04:00
atan_lut.mif add coregen files 2017-04-14 16:29:33 -04:00
atan_lut.ncf add coregen files 2017-04-14 16:29:33 -04:00
atan_lut.ngc add coregen files 2017-04-14 16:29:33 -04:00
atan_lut.sym add coregen files 2017-04-14 16:29:33 -04:00
atan_lut.v verilog init 2017-04-03 12:52:03 -04:00
atan_lut.veo add coregen files 2017-04-14 16:29:33 -04:00
atan_lut.vhd add coregen files 2017-04-14 16:29:33 -04:00
atan_lut.vho add coregen files 2017-04-14 16:29:33 -04:00
atan_lut.xco add coregen files 2017-04-14 16:29:33 -04:00
atan_lut.xise add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier_flist.txt add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier_readme.txt add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier_xmdf.tcl add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier.asy add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier.gise add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier.ncf add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier.ngc add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier.sym add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier.v verilog init 2017-04-03 12:52:03 -04:00
complex_multiplier.veo add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier.vhd add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier.vho add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier.xco add coregen files 2017-04-14 16:29:33 -04:00
complex_multiplier.xise add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut_flist.txt add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut_xmdf.tcl add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut.asy add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut.gise add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut.mif add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut.ncf add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut.ngc add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut.sym add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut.v verilog init 2017-04-03 12:52:03 -04:00
deinter_lut.veo add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut.vhd add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut.vho add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut.xco add coregen files 2017-04-14 16:29:33 -04:00
deinter_lut.xise add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0_flist.txt add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0_readme.txt add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0_xmdf.tcl add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0.asy add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0.gise add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0.ncf add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0.ngc add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0.sym add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0.v verilog init 2017-04-03 12:52:03 -04:00
div_gen_v3_0.veo add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0.vhd add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0.vho add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0.xco add coregen files 2017-04-14 16:29:33 -04:00
div_gen_v3_0.xise add coregen files 2017-04-14 16:29:33 -04:00
rot_lut.asy add coregen files 2017-04-14 16:29:33 -04:00
rot_lut.gise add coregen files 2017-04-14 16:29:33 -04:00
rot_lut.mif add coregen files 2017-04-14 16:29:33 -04:00
rot_lut.ncf add coregen files 2017-04-14 16:29:33 -04:00
rot_lut.ngc add coregen files 2017-04-14 16:29:33 -04:00
rot_lut.sym add coregen files 2017-04-14 16:29:33 -04:00
rot_lut.v verilog init 2017-04-03 12:52:03 -04:00
rot_lut.veo add coregen files 2017-04-14 16:29:33 -04:00
rot_lut.vhd add coregen files 2017-04-14 16:29:33 -04:00
rot_lut.vho add coregen files 2017-04-14 16:29:33 -04:00
rot_lut.xco add coregen files 2017-04-14 16:29:33 -04:00
rot_lut.xise add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0_flist.txt add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0_readme.txt add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0_xmdf.tcl add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0.asy add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0.gise add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0.ncf add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0.ngc add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0.sym add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0.v verilog init 2017-04-03 12:52:03 -04:00
viterbi_v7_0.veo add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0.vhd add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0.vho add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0.xco add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0.xise add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0rombram.mif add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0romlifo.mif add coregen files 2017-04-14 16:29:33 -04:00
viterbi_v7_0romwe.mif add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1_flist.txt add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1_readme.txt add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1_xmdf.tcl add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1.asy add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1.gise add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1.ncf add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1.ngc add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1.sym add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1.v verilog init 2017-04-03 12:52:03 -04:00
xfft_v7_1.veo add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1.vhd add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1.vho add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1.xco add coregen files 2017-04-14 16:29:33 -04:00
xfft_v7_1.xise add coregen files 2017-04-14 16:29:33 -04:00