openofdm/verilog/coregen/atan_lut.sym
2017-04-14 16:29:33 -04:00

19 lines
1.0 KiB
XML

<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="atan_lut">
<symboltype>BLOCK</symboltype>
<timestamp>2016-11-8T19:48:42</timestamp>
<pin polarity="Input" x="0" y="80" name="addra[7:0]" />
<pin polarity="Input" x="0" y="272" name="clka" />
<pin polarity="Output" x="576" y="80" name="douta[8:0]" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">atan_lut</text>
<rect width="512" x="32" y="32" height="640" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[7:0]" />
<line x2="32" y1="272" y2="272" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[8:0]" />
</graph>
</symbol>