mirror of
https://github.com/jhshi/openofdm.git
synced 2024-12-20 14:13:19 +00:00
94 lines
2.7 KiB
Plaintext
94 lines
2.7 KiB
Plaintext
##############################################################
|
|
#
|
|
# Xilinx Core Generator version 12.2
|
|
# Date: Mon Nov 7 19:11:21 2016
|
|
#
|
|
##############################################################
|
|
#
|
|
# This file contains the customisation parameters for a
|
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
|
# that you do not manually alter this file as it may cause
|
|
# unexpected and unsupported behavior.
|
|
#
|
|
##############################################################
|
|
#
|
|
# BEGIN Project Options
|
|
SET addpads = false
|
|
SET asysymbol = true
|
|
SET busformat = BusFormatAngleBracketNotRipped
|
|
SET createndf = false
|
|
SET designentry = Verilog
|
|
SET device = xc3sd3400a
|
|
SET devicefamily = spartan3adsp
|
|
SET flowvendor = Foundation_ISE
|
|
SET formalverification = false
|
|
SET foundationsym = false
|
|
SET implementationfiletype = Ngc
|
|
SET package = fg676
|
|
SET removerpms = false
|
|
SET simulationfiles = Behavioral
|
|
SET speedgrade = -5
|
|
SET verilogsim = true
|
|
SET vhdlsim = true
|
|
# END Project Options
|
|
# BEGIN Select
|
|
SELECT Block_Memory_Generator family Xilinx,_Inc. 4.2
|
|
# END Select
|
|
# BEGIN Parameters
|
|
CSET additional_inputs_for_power_estimation=false
|
|
CSET algorithm=Minimum_Area
|
|
CSET assume_synchronous_clk=true
|
|
CSET byte_size=9
|
|
CSET coe_file=/home/jinghaos/projects/jammer/uhd/fpga-src/usrp2/custom/rot_lut.coe
|
|
CSET collision_warnings=ALL
|
|
CSET component_name=rot_lut
|
|
CSET disable_collision_warnings=false
|
|
CSET disable_out_of_range_warnings=false
|
|
CSET ecc=false
|
|
CSET ecctype=No_ECC
|
|
CSET enable_a=Always_Enabled
|
|
CSET enable_b=Always_Enabled
|
|
CSET error_injection_type=Single_Bit_Error_Injection
|
|
CSET fill_remaining_memory_locations=false
|
|
CSET load_init_file=true
|
|
CSET memory_type=Dual_Port_ROM
|
|
CSET operating_mode_a=WRITE_FIRST
|
|
CSET operating_mode_b=WRITE_FIRST
|
|
CSET output_reset_value_a=0
|
|
CSET output_reset_value_b=0
|
|
CSET pipeline_stages=0
|
|
CSET port_a_clock=100
|
|
CSET port_a_enable_rate=100
|
|
CSET port_a_write_rate=0
|
|
CSET port_b_clock=100
|
|
CSET port_b_enable_rate=100
|
|
CSET port_b_write_rate=0
|
|
CSET primitive=8kx2
|
|
CSET read_width_a=32
|
|
CSET read_width_b=32
|
|
CSET register_porta_input_of_softecc=false
|
|
CSET register_porta_output_of_memory_core=false
|
|
CSET register_porta_output_of_memory_primitives=false
|
|
CSET register_portb_output_of_memory_core=false
|
|
CSET register_portb_output_of_memory_primitives=false
|
|
CSET register_portb_output_of_softecc=false
|
|
CSET remaining_memory_locations=0
|
|
CSET reset_memory_latch_a=false
|
|
CSET reset_memory_latch_b=false
|
|
CSET reset_priority_a=CE
|
|
CSET reset_priority_b=CE
|
|
CSET reset_type=SYNC
|
|
CSET softecc=false
|
|
CSET use_byte_write_enable=false
|
|
CSET use_error_injection_pins=false
|
|
CSET use_regcea_pin=false
|
|
CSET use_regceb_pin=false
|
|
CSET use_rsta_pin=false
|
|
CSET use_rstb_pin=false
|
|
CSET write_depth_a=512
|
|
CSET write_width_a=32
|
|
CSET write_width_b=32
|
|
# END Parameters
|
|
GENERATE
|
|
# CRC: eb4434e9
|