Jinghao Shi 556794ae2e add coregen files

2017-04-14 16:29:33 -04:00

..

coregen

add coregen files

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sim_out

add sim_out dir

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usrp2

verilog init

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Xilinx/12.2/ISE_DS/ISE/verilog/src

verilog init

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atan_lut.coe

verilog init

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atan_lut.mif

verilog init

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bits_to_bytes.v

verilog init

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calc_mean.v

verilog init

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common_defs.v

verilog init

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common_params.v

readme

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complex_mult.v

verilog init

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complex_to_mag_sq.v

verilog init

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complex_to_mag.v

use delayT

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crc32.v

verilog init

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deinter_lut.coe

verilog init

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deinter_lut.mif

verilog init

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deinterleave.v

verilog init

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delay_sample.v

verilog init

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delayT.v

verilog init

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demodulate.v

verilog init

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descramble.v

verilog init

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divider.v

verilog init

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dot11_modules.list

verilog init

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dot11_tb.v

enlarge num_sample

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dot11.v

readme

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equalizer.v

fix polarity pattern

2017-04-14 11:00:01 -04:00

ht_sig_crc.v

verilog init

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Makefile

makefile

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moving_avg.v

verilog init

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ofdm_decoder.v

verilog init

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phase.v

fix comment

2017-04-14 11:00:12 -04:00

power_trigger.v

working

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rand_gen_tb.v

verilog init

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rand_gen.v

verilog init

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rate_to_idx.v

verilog init

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rot_lut.coe

verilog init

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rot_lut.mif

verilog init

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rotate.v

rotate

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stage_mult.v

verilog init

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sync_long.v

variable name

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sync_short.v

refactor name

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viterbi.v

verilog init

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