7 Commits

Author	SHA1	Message	Date
mmehari	85b1adbec7	bug fix: increase phase calculation delay by 1 CLK	2022-01-04 22:22:00 +01:00
mmehari	36c738fe98	phase estimation update: quadrant quantization from 256 slices -> 512 slices	2022-01-04 22:15:16 +01:00
mmehari	82d2d456e5	keep significant bits while performing division during phase calculation	2022-01-04 22:11:50 +01:00
mmehari	d9649eb614	phase register size reduction: 32bit -> 16bit	2022-01-04 22:10:36 +01:00
Xianjun Jiao	d7f5806790	fix the atan_addr overflow issue (phase.v)	2020-08-29 14:48:38 +02:00
Jinghao Shi	47577f7099	fix comment	2017-04-14 11:00:12 -04:00
Jinghao Shi	9edf1899bd	verilog init	2017-04-03 12:52:03 -04:00