10 Commits

Author	SHA1	Message	Date
Xianjun Jiao	e65ee43101	Make some basic block simpler and its delay more deterministic	2023-01-09 14:47:34 +01:00
Xianjun Jiao	a1e1e0090b	Add threshold_scale and enable it by default: ... sync short works at low SNR and the receiver sensitivity is better	2023-01-09 14:43:34 +01:00
thavinga	cb6b566d5f	Move all signal logging to dot11_tb.v	2022-05-16 09:33:19 +02:00
mmehari	53679a107f	integer division rounding fix during phase offset calculation	2022-01-04 22:12:45 +01:00
mmehari	d9649eb614	phase register size reduction: 32bit -> 16bit	2022-01-04 22:10:36 +01:00
Xianjun Jiao	539133f453	make the code more testbench friendly	2020-09-02 21:59:37 +02:00
Xianjun Jiao	2643844f2f	necessary bug fixes and improvements for openwifi	2019-12-10 13:31:16 +01:00
weiliu	10ff8da3d7	port dot11 to zynq	2019-12-10 14:09:31 +01:00
Jinghao Shi	8375779a03	refactor name	2017-04-07 11:36:41 -04:00
Jinghao Shi	9edf1899bd	verilog init	2017-04-03 12:52:03 -04:00