Commit Graph

4 Commits

Author SHA1 Message Date
Xianjun Jiao
1043429762 signal watchdog only work while rssi above threshold:
power_trigger valid
2023-01-09 15:31:52 +01:00
Xianjun Jiao
54bdff7348 Make minimum pkt length configurable for signal_watchdog 2023-01-09 15:30:20 +01:00
Xianjun Jiao
75979e165a Add fake random +/-1 input while input are 0s:
to avoid receiver reset during self-rx-muting (packet sending)
2023-01-09 15:29:33 +01:00
Xianjun Jiao
f08c76ca3d Add signal_watchdog module to prevent fake demod in early phase:
1. If strong DC or low frequency sing wave like signal (suspect it is generated by ad9361 during some self-calibration like operation), put the receiver into reset
2. If the signal/header is valid, but the packet length is abnormal (signal_len<14 || signal_len>max_signal_len_th), reset the receiver
2022-03-15 16:03:40 +01:00