5 Commits

Author	SHA1	Message	Date
Xianjun Jiao	bf043af712	change the latency of divider from automatic 60 clocks to the original 36 clock	2020-09-02 16:49:59 +02:00
Xianjun Jiao	6a0073ee58	remove debug	2020-06-12 10:24:59 +02:00
Xianjun Jiao	abbe9ecde9	extend support to zcu102/Zynq MPSoC ultra_scale	2020-04-27 15:46:16 +02:00
Jinghao Shi	556794ae2e	add coregen files	2017-04-14 16:29:33 -04:00
Jinghao Shi	9edf1899bd	verilog init	2017-04-03 12:52:03 -04:00