Commit Graph

835 Commits

Author SHA1 Message Date
Stefan Kalkowski
f939b9ffb5 base-hw: print addr as hex value in cache warning
Ref #4207
2021-07-28 11:25:21 +02:00
Sebastian Sumpf
4b10aa94ec base-hw: save/restore fpcr register for ARM_V8
The floating-point (fpcr) control register is user land accessible and
controls, for example, rounding mode.

fixes #3723 and related to #4213
2021-07-28 11:25:20 +02:00
Christian Helmuth
ece33d37f8 depot: update recipe hashes 2021-06-25 11:46:37 +02:00
Stefan Kalkowski
e7067050be base: extend cache maintainance functionality
Introduce two new cache maintainance functions:
* cache_clean_invalidate_data
* cache_invalidate_data
used to flush or invalidate data-cache lines.

Both functions are typically empty, accept for the ARM architecture.
The commit provides implementations for the base-hw kernel, and Fiasco.OC.

Fixes #4207
2021-06-25 11:43:41 +02:00
Christian Helmuth
1d52bd017d depot: update recipe hashes 2021-05-28 14:16:46 +02:00
Stefan Kalkowski
9f099bd61c base-hw: use generalized util/array.h
Issue #4170
2021-05-28 14:16:45 +02:00
Alexander Boettcher
509e5aa776 platform(x86): report features via platform_info
Report via platform_info the capabilities of the kernel, e.g. ACPI and MSI.

With the commit the try-catch pattern on IRQ session creation by the platform
driver is avoided.

Issue #4016
2021-05-28 14:16:44 +02:00
Christian Helmuth
777923f9bd depot: update recipe hashes 2021-05-10 11:18:12 +02:00
Norman Feske
516a9a6925 depot: update recipe hashes 2021-05-05 11:35:31 +02:00
Christian Prochaska
c4e3d3dbc4 hw: fix build error with gcc 10
Fixes #4115
2021-05-05 11:35:30 +02:00
Norman Feske
efbed6f7bf depot: update recipe hashes 2021-04-20 12:10:58 +02:00
Norman Feske
dc89ebf978 core: kernel-agnostic 'Mapping' type
This patch unifies the core-internal 'Mapping' type across all base
platforms.

As one minor downside on seL4, the diagnostic error messages when
observing faults other than page faults no longer print the faulting
thread and PD names.

Issue #2243
2021-04-20 12:10:57 +02:00
Norman Feske
468e7a825c base/cache.h: rename Cache_attribute to Cache
The short name is better because the type will become prominently
visible at the API.

Issue #2243
2021-04-20 12:10:31 +02:00
Norman Feske
0f9cb72cfa depot: update recipe hashes 2021-03-29 13:46:49 +02:00
Jean-Adrien DOMAGE
32169cd137 add I2c driver for imx8q based platform
This commit introduces a new i2c driver for the imx8q_evk based platform.

Fixes #4052
2021-03-29 13:45:24 +02:00
Norman Feske
5c5b56d1e0 depot: update recipe hashes 2021-03-12 12:08:24 +01:00
Sebastian Sumpf
6223ae4413 riscv: Interrupt controller support
- Enable the "platform-level interrupt controller" PLIC on base-hw
- The RISC-V specification offers only a register description, but no
  layout for the register set. This implies the layout is platform
  dependent, and therefore, implemented separately for Qemu

issue #4042
2021-03-12 12:01:38 +01:00
Norman Feske
aa0a98bd43 base-foc/hw: avoid use of placement new operator
Fixes #2106
2021-03-12 12:01:38 +01:00
Norman Feske
c68443e2eb base-hw: support packaging of multi-arch boards
With this patch, the board/<name>/arch property file can have multiple
lines where each line denotes an instruction-set architecture supported
for the board.

Issue #4019
Fixes #4034
2021-03-12 12:01:36 +01:00
Sebastian Sumpf
d4b58b689c base-hw: fix RISC-V duration calculation
Simplify calculation of Timer::_duration, the old implementation caused
the time running backwards sometimes. This makes
'nic_router_dhcp_*' and 'event_filter' run scripts succeed.

issue #4021
2021-03-12 12:01:36 +01:00
Christian Helmuth
0afd3db894 depot: update recipe hashes 2021-02-25 11:24:23 +01:00
Sebastian Sumpf
f68e655312 mk: link core to library archive instead of .o file
Do not link base and core libraries into on large relocatable .o file,
which is linked later to core - causing long link times. Create an
independent library archive out of the base and core libraries that can
be linked faster.

issue #4027
2021-02-23 12:17:04 +01:00
Norman Feske
64165d829e depot: update recipe hashes 2021-02-23 12:07:18 +01:00
Christian Helmuth
219809ffed base: refactor VM/vCPU API
Issue #3554
2021-02-23 12:07:18 +01:00
Sebastian Sumpf
ca777fe93f riscv: add riscv_qemu base-hw recipe
issue #4021
2021-02-23 12:07:16 +01:00
Sebastian Sumpf
ccd9ba4161 riscv: move CPU header from base-hw to base
issue #4021
2021-02-23 12:07:16 +01:00
Sebastian Sumpf
f5cd12dcf9 base/base-hw: unify startup library builds
- Use 'select_from_repositories' for crt0.s of startup library
- Move RISC-V crt0.s to base (where the other archs are located)

issue #4019
2021-02-23 12:07:15 +01:00
Norman Feske
db3f86d603 base-hw: avoid double slashes in path names 2021-02-23 12:02:45 +01:00
Norman Feske
fa68325a57 base-hw: streamline extraction of depot archives
This patch simplifies the packaging of the base-hw kernel for a given
board, in particular when the board support is hosted as an external
repository such as genode-world. Regardless of where the board-support
is hosted, the content.mk file becomes as simple as:

  include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc

The board name is automatically inferred from the path of the src
recipe. The architecture is determined from board/<name>/arch files,
following the pattern of the image_link_address. The attempt to build a
base-hw-<board> binary archive for the wrong architecture is now
gracefully handled by skipping all targets (using the REQUIRES
mechanism).

Besides the improved convenience, the patch results in depot archives
that are much closer tailored to the actual board by omitting files for
architectures that are not used by the board. E.g., the src/base-hw-pc
archive does not contain any ARM-related content.

The patch also restores the package builds for core/bootstrap object
files as a follow-up fix of "base: remove SPEC variables of boards",
which happened to left 'BOARD' undefined in the src archives.

Fixes #4019
2021-02-23 12:02:45 +01:00
Sebastian Sumpf
fd0e6685fc riscv: Use Qemu and update to ISA v1.10
- remove Spike/BBL support in favour of Qemu (>=4.2.1)
- add 'riscv_qemu' board, remove 'spike' board'
- update to privileged ISA v1.10 (from v1.9.1)
- use direct system calls for privileged core threads (they call into
  the kernel and don't use mode changing system calls, i.e. 'ecall',
  semantics)
- use 'OpenSBI' semtantics for SBI calls (to machine mode) instead of
  BBL

issue #4012
2021-02-23 12:02:44 +01:00
Norman Feske
493924a35e base-hw: coding style
Improve consistency with the other base repositories, in particular

- Indentation of class initializers
- Vertical whitespace around control-flow statements
- Preferably place control-flow statements (return, break, continue) at
  beginning of a line
- Placing the opening brace of a namespace at the end of line
- Placing the opening brace of a class at a new line
- Removing superfluous braces around single statements
- Two empty lines between methods/functions in implementation files
2021-02-23 12:02:41 +01:00
Norman Feske
8cc2662aac Remove support for the Muen separation kernel
Fixes #3995
Fixes #3994
2021-02-23 11:55:44 +01:00
Norman Feske
a981fb864c depot: update recipe hashes 2021-01-25 14:00:43 +01:00
Norman Feske
c4cf9b6e6d base-hw: introduce board-property directories
This patch moves the bootstrap-link-address information from the
tool/run/boot_dir/hw file to board-specific property files that can be
accessed by using the board as key. This eliminates the need to
customize boot_dir/hw when hosting board-support in an external
repository.

Fixes #3998
2021-01-25 14:00:43 +01:00
Piotr Tworek
8f6b934caa base-hw: Fully define _crt0_start_stack value on arm_64
The _crt0_start_stack label points to a memory location containing the
size of the bootstrap stack. On AArch64 this should be an 8 byte value,
but the code only only defines half of those using asm .long statement.
The other half is expected to be 0, which is true when using GNU as.
This is not the case when using clang's integrated as however. Since
_crt0_stack_size is defined inside .text section clang uses 0xd503201f
value (aarch64 nop instruction) to fill the extra 4 bytes.

Fix this minor incompatibility by explicitly defining both halfs of
this 8 byte quantity.

Fixes #3987
2021-01-25 14:00:43 +01:00
Norman Feske
1ccf8a280c base-hw: simplify board support in external repo
Avoid use of REP_DIR in *.mk files to simplify the use of these files as
templates for a board hosted in a separate repository.

Use REP_INC_DIR for searching headers, thereby considering headers
hosted in an external repository.

Issue #3168
2021-01-25 13:58:10 +01:00
Stefan Kalkowski
bdd923406f base: remove SPEC variables of boards (fix #3971)
* Remove SPEC declarations from mk/spec
* Remove all board-specific REQUIRE declaratiions left
* Replace [have_spec <board>] run-script declarations with have_board where necessary
* Remove addition of BOARD variable to SPECS in toplevel Makefile
* Move board-specific directories in base-hw out of specs
2021-01-25 13:58:09 +01:00
Pirmin Duss
a4d5687510 base-hw: allow out of tree imx8 platforms
Issue #3911
2021-01-25 13:58:09 +01:00
Alexander Boettcher
2b0170fb6a base-hw: ack thread capability on construction
Fixes #3982
2021-01-25 13:58:09 +01:00
Norman Feske
f57519397b Remove Pd_session::Native_pd definition from API
This type can be a forward declaration in the public API because its
definition is required only in kernel-specific code.

Fixes #3979
2021-01-25 12:51:54 +01:00
Tomasz Gajewski
98798f18b5 Fix minor inconsistencies in mk files
Fixes #3972
2021-01-25 12:50:54 +01:00
Christian Helmuth
1bef11accf depot: update recipe hashes 2020-12-18 09:10:52 +01:00
Christian Helmuth
f2e0c164c2 depot: update recipe hashes 2020-11-27 09:21:06 +01:00
Alexander Boettcher
774b1f4277 base: remove Thread_deprecated
Fixes #3954
2020-11-27 09:19:08 +01:00
Piotr Tworek
5db2971903 base-hw/arm_v7a: Mark r1 as out in Kernel::call64
In case of arm_v7a Kernel::call64 the syscall will use both r0 and r1 as
output registers. Unfortunately the inline asm does not reflect this and
only r0 is explicitly specified as output. GCC manages to produce output
which we'd like to see. Clang on the other hand takes adventage of the fact
r1 should not be touched by swi and produces fewer instructions which do
what the code describes, but not what we actually want.

Basically the code which we want and is generated by GCC is:
  svc     0
  mov     r2, r0
  mov     r0, r1
  mov     r1, r2
  bx      lr

Clang on the other hand generates correct assembly given the code, but
incorrect given what the function is supposed to do:
  svc     0
  mov     r1, r0
  mov     r0, #0
  bx      lr

Both GCC and clang generate the same, expected assembly output when r1
is marked as output register from the inline asm swi call.

Fixes #3951
2020-11-27 09:19:08 +01:00
Piotr Tworek
50ab86cd72 base-hw: Remove unused rdtsc function for x86_64
This function has no callers. Clang warns about this.

Issue #3950
2020-11-27 09:19:08 +01:00
Piotr Tworek
a892018926 base-hw: Define Entry function as noreturn.
Right now the code marks specific instance of this function as noreturn.
It then tries to initialize it using a value that has the same type,
except for the noreturn part. GCC does not care, but clang complains this
technically assigns the value of entry from incompatible pointer type.

Fix this by defining Entry function as no return.

Issue #3938
2020-11-23 12:02:59 +01:00
Piotr Tworek
1643d623e4 base-hw: Fix warning about unused lambda capture
The lambda function passed to Board::Vm_page_table_array does not
actually use "this" for anything. GCC does not warn about this, but
clang does. Remove the extra capture to make clang happy.

Issue #3938
2020-11-23 12:02:59 +01:00
Piotr Tworek
9b84a8a402 base-hw: Add semicolons after [[fallthrough]]
GCC doesn't care, but clang complains if [[fallthrough]] is not followed
by a semicolon. Existing code is also not consitent in this regard. Lets
just fix it to make clang happy.

Issue #3938
2020-11-23 12:02:59 +01:00
Stefan Kalkowski
7298b00013 base-hw: make ARMv7/v8 hypervisor smp ready
* Introduce hypervisor-stack per CPU
* Introduce host world context per CPU
* Mark EL2 translation table memory as inner shareable
* The VMID is not bound to a single VCPU, but to the Vm_session as a whole
* Set affinity of the VCPU accordingly
* Add VMPIDR to VM state

Ref #3926
2020-11-23 12:02:58 +01:00