Chuanhong Guo cf50f72069 ath79: ar913x: fix eth pll register
PLL for eth0 internal clock on ar913x is at 0x18050014
and AR913X_ETH0_PLL_SHIFT is 20 instead of 17

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-08-13 08:37:19 +02:00
..
2018-08-08 08:11:11 +02:00
2018-08-09 18:44:57 +02:00
2018-08-08 08:11:11 +02:00
2018-08-08 08:11:11 +02:00
2018-05-17 07:40:19 +02:00
2018-08-08 08:11:11 +02:00
2018-08-08 08:11:11 +02:00
2018-08-08 08:11:11 +02:00
2018-08-08 08:11:11 +02:00
2018-08-08 08:11:11 +02:00
2018-06-08 12:19:49 +02:00
2018-08-08 08:11:11 +02:00
2018-08-08 08:11:11 +02:00
2018-08-08 08:11:11 +02:00
2018-08-08 08:11:11 +02:00
2018-08-08 08:11:11 +02:00
2018-08-08 08:11:11 +02:00