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ath79: fix PLL settings for QCA955x

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This adds PLL settings for the ethernet ports of the TP-Link TL-WR1043
v2/v3 and the Openmesh OM5P-AC-v2.

We also change the PLL-settings in the qca9557.dtsi to match the ones
used as default on the ar71xx target.

As of 4b9680f138 those devices have broken ethernet ports as the default
PLL settings defined in the QCA9557.dtsi are applied which are off for
those devices.

Signed-off-by: David Bauer <mail@david-bauer.net>
This commit is contained in:
David Bauer 2018-08-09 16:10:13 +02:00 committed by Kevin Darbyshire-Bryant
parent 995a1ba841
commit 6555612783
3 changed files with 10 additions and 2 deletions
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4
target/linux/ath79/dts/qca9557.dtsi
View File

@ -298,7 +298,7 @@
pll-reg = <0 0x28 0>;
pll-handle = <&pll>;
pll-data = <0x82000101 0x80000101 0x80001313>;
pll-data = <0x16000000 0x00000101 0x00001616>;
phy-mode = "rgmii";
resets = <&rst 9>;
@ -316,7 +316,7 @@
pll-reg = <0 0x48 0>;
pll-handle = <&pll>;
pll-data = <0x82000101 0x80000101 0x80001313>;
pll-data = <0x16000000 0x00000101 0x00001616>;
phy-mode = "sgmii";
resets = <&rst 13>;

4
target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts
View File

@ -155,6 +155,8 @@
&eth0 {
status = "okay";
pll-data = <0x82000101 0x80000101 0x80001313>;
phy-handle = <&phy4>;
phy-mode = "rgmii";
};
@ -162,6 +164,8 @@
&eth1 {
status = "okay";
pll-data = <0x03000101 0x80000101 0x80001313>;
phy-handle = <&phy1>;
phy-mode = "sgmii";
};

4
target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd.dtsi
View File

@ -155,6 +155,8 @@
&eth0 {
status = "okay";
pll-data = <0x56000000 0x00000101 0x00001616>;
mtd-mac-address = <&uboot 0x1fc00>;
mtd-mac-address-increment = <1>;
phy-handle = <&phy0>;
@ -163,6 +165,8 @@
&eth1 {
status = "okay";
pll-data = <0x03000101 0x00000101 0x00001616>;
mtd-mac-address = <&uboot 0x1fc00>;
fixed-link {