mirror of
https://github.com/openwrt/openwrt.git
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74df6ce9db
Hardware:
SoC: MT7981b
RAM: 256 MB
Flash: 128 MB SPI NAND
Ethernet:
1x 2.5Gbps (rtl8221b)
1x 1Gbps (integrated phy)
WiFi: 2x2 MT7981
Buttons: Reset, WPS
LED: 1x multicolor
Solder on UART:
- remove rubber ring on the bottom
- remove screws
- pull up the cylinder, maybe help by push on an ethernet socket with a screwdriver
- remove the (3) screws holding the board in the frame
- remove the board from the frame to get to the screws for the silver, flat heat shield
- remove the (3) screws holding the heat shield
- solder UART pins to the back of the board
- make sure to have the pins point out on side with the black, finned heat spread
- the markings for the pins are going to be below the silver heat shield
- Vcc is not needed
If you don't intend on using the UART outside of the installation process, you might not
want to solder:
- carefully scrape off the thin layer of epoxy on the holes (not the copper)
- place your pin header with the UART attached in the holes
- the pins, starting with the one closest to the socket:
- Vcc (not required)
- GND
- RX
- TX
- either wedge the header or hold it with your fingers so that the pins stay in contact with the board
Installation (UART):
- attach an Ethernet cable to the 1Gbps port (black) on the router
- hold the reset button while powering the router
- press CTRL-C or wait for the timeout to get to the U-Boot prompt
- prepare a TFTP server on the network to supply ..-initramfs-kernel.bin
- use 'tftpboot' in the U-Boot shell to pull the image
- boot the image using 'bootm'
- push the ..-sysupgrade to the router using your preferred method
- perform the upgrade with 'sysupgrade -n'
There is a recovery mechanism that involves fetching a file called 'recovery.bin' but that is not understood yet.
Signed-off-by: Leon M. Busch-George <leon@georgemail.eu>
(cherry picked from commit 20e4a18feb
)
215 lines
3.8 KiB
Plaintext
215 lines
3.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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#include "mt7981.dtsi"
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/ {
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model = "Cudy M3000 v1";
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compatible = "cudy,m3000-v1", "mediatek,mt7981-spim-snand-rfb";
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aliases {
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ethernet0 = &gmac0;
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label-mac-device = &gmac0;
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led-boot = &led_status;
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led-failsafe = &led_status;
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led-running = &led_status;
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led-upgrade = &led_status;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&pio 1 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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wps {
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label = "wps";
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gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_status: internet-white {
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function = LED_FUNCTION_WAN_ONLINE;
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color = <LED_COLOR_ID_WHITE>;
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gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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};
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internet-red {
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function = LED_FUNCTION_WAN_ONLINE;
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color = <LED_COLOR_ID_RED>;
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gpios = <&pio 4 GPIO_ACTIVE_LOW>;
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};
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wan {
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function = LED_FUNCTION_WAN;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&pio 5 GPIO_ACTIVE_LOW>;
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};
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lan {
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function = LED_FUNCTION_LAN;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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ð {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins>;
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "2500base-x";
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phy-handle = <&rtl8221b_phy>;
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/* the MAC address assignment using nvmem-cells doesn't work, so it's done through 02_network */
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "gmii";
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phy-handle = <&int_gbe_phy>;
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nvmem-cell-names = "mac-address";
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nvmem-cells = <&macaddr_bdinfo_de00 0>;
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};
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};
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&mdio_bus {
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rtl8221b_phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <1>;
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reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
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interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
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reset-assert-us = <100000>;
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reset-deassert-us = <100000>;
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_flash_pins>;
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status = "okay";
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spi_nand: spi_nand@0 {
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compatible = "spi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <52000000>;
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spi-tx-buswidth = <4>;
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spi-rx-buswidth = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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mediatek,nmbm;
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mediatek,bmt-max-ratio = <1>;
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mediatek,bmt-max-reserved-blocks = <64>;
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partition@0 {
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label = "BL2";
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reg = <0x0000000 0x0100000>;
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read-only;
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};
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partition@100000 {
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label = "u-boot-env";
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reg = <0x0100000 0x0080000>;
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};
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factory: partition@180000 {
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label = "Factory";
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reg = <0x0180000 0x0200000>;
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read-only;
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};
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bdinfo: partition@380000 {
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label = "bdinfo";
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reg = <0x0380000 0x0040000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_bdinfo_de00: macaddr@de00 {
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#nvmem-cell-cells = <1>;
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compatible = "mac-base";
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reg = <0xde00 0x6>;
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};
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};
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};
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partition@3c0000 {
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label = "FIP";
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reg = <0x03c0000 0x0200000>;
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};
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partition@5c0000 {
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label = "ubi";
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reg = <0x05c0000 0x4000000>;
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};
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};
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};
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};
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&pio {
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spi0_flash_pins: spi0-pins {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
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};
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conf-pd {
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pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
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};
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};
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};
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&wifi {
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status = "okay";
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mediatek,mtd-eeprom = <&factory 0x0>;
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};
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