A Locking bug in the packet receive path was introduced with PR
#4973. The following patch prevents the driver from locking
after a few minutes with an endless flow of
[ 1434.185085] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000f8
[ 1434.208971] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc
[ 1434.794800] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc
[ 1435.049187] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
When initialising the driver, check if the RTL8231 chip is actually
present at the specified address. If the READY_CODE value does not match
the expected value, return -ENXIO to fail probing.
This should help users to figure out which address an RTL8231 is
configured to use, if measuring pull-up/-down resistors is not an
option.
On an unsuccesful probe, the driver will log:
[ 0.795364] Probing RTL8231 GPIOs
[ 0.798978] rtl8231_init called, MDIO bus ID: 30
[ 0.804194] rtl8231-gpio rtl8231-gpio: no device found at bus address 30
When a device is found, only the first two lines will be logged:
[ 0.453698] Probing RTL8231 GPIOs
[ 0.457312] rtl8231_init called, MDIO bus ID: 31
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
The SMI bus ID for RTL8231 currently defaults to 0, and can be
overridden from the devicetree. However, there is no value check on the
DT-provided value, aside from masking which would only cause value
wrap-around.
Change the driver to always require the "indirect-access-bus-id"
property, as there is no real reason to use 0 as default, and perform a
sanity check on the value when probing. This allows the other parts of
the driver to be simplified a bit.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Set the gpio_chip.base to -1 to use automatic GPIO line indexing.
Setting base to 0 or a positive number is deprecated and should not be
used.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
The RTL8231's gpio_chip.ngpio was set to 36, which is the largest valid
GPIO index. Fix the allowed number of GPIOs by setting ngpio to 37, the
actual line count.
Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Replace magic values with more self-descriptive code now that I start
to understand more about the design of the PHY (and MDIO controller).
Remove one line before reading RTL8214FC internal PHY id which turned
out to be a no-op and can hence safely be removed (confirmed by
INAGAKI Hiroshi[1])
[1]: df8e6be59a (r66890713)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Instead of directly calling SoC-specific functions in order to access
(paged) MII registers or MMD registers, create infrastructure to allow
using the generic phy_*, phy_*_paged and phy_*_mmd functions.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* Add missing Clause-45 write support for rtl931x
* Switch to use helper functions in all Clause-45 access functions to
make the code more readable.
* More meaningful/unified debugging output (dynamic kprintf)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Import commit ("c6af53f038aa3 net: mdio: add helpers to extract clause
45 regad and devad fields") from Linux 5.17 to allow making the MDIO
code in the ethernet driver more readable.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Using the led-set attribute of a port in the dts we allow configuration
of the port leds. Each led-set is being defined in the led-set configuration
of the .dts, giving a specific configuration to steer the port LEDs via a serial
connection.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL8221B PHY is a newer version of the RTL8226, also supporting
2.5GBit Ethernet. It is found with RTL931X devices such as the
EdgeCore ECS4125-10P
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Both the Aquantia AQR113c and the RTL8226 PHYs in the Zyxel XGS1250 and the
Zyxel XGS1210 require special polling configuration settings in the
RTL930X_SMI_10GPHY_POLLING_REGxx_CFG configuration registers. Set them.
Additionally, for RTL 1GBit phys set the RTL930X_SMI_PRVTE_POLLING_CTRL bits
in the poll mask.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
For SFP slots on the RTL9302, the link status is not correctly detected.
Use the link media status instead.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We add the RTL931X sub-target with kernel configuration for
a dual core MIPS InterAptive CPU.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We add HW support routines for the RTL931X SoC family for handling
the Packet Inspection Engine, L2 table handling and STP aging.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We need to store and restore MC memberships in HW when a port joins or
leaves a bridge as well as when it is enabled or disabled, as these
properties should not change in these situations.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
In order to receive STP information at the kernel level, we make sure
that all Bridge Protocol Data Units are copied to the CPU-Port.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Instead of a generic L2 aging configuration function with complex
logic, we implement an individual function for all SoC types.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Add functionality to enable or disable L2 learning offload and port flooding
for RTL83XX.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Adds the DSA API for bridge configuration (flooding, L2 learning,
and aging) offload as found in Linux 5.12 so that we can implement
it in our drivver.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This adds LAG support for all 4 SoC families, including support
ofr the use of different distribution algorithm for the load-
balancing between individual links.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Add the LAG configuration API for DSA as found in Linux 5.12 so that we
can implement it in the dsa driver.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Use setting functions instead of register numbers in order to clean up the code.
Also use enums to define inner/outer VLAN types and the filter type.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The ZyXEL XGS1250-12 Switch is a 11 + 1 port multi-GBit switch with
8 x 1000BaseT, 3 x 1000/2500/5000/10000BaseT Ethernet ports and
1 SFP+ module slot.
Hardware:
- RTL9302B SoC
- Macronix MX25L12833F (16MB flash)
- Nanja NT5CC64M16GP-1 (128MB DDR3 SDRAM)
- RTL8231 GPIO extender to control the port LEDs
- RTL8218D 8x Gigabit PHY
- Aquantia AQR113c 1/2.5/5/10 Gigabit PHYs
- SFP+ 10GBit slot
Power is supplied via a 12V 2A standard barrel connector. At the
right side behind the grid is UART serial connector. A Serial
header can be connected to from the outside of the switch trough
the airvents with a standard 2.54mm header.
Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial
connection is via 115200 baud, 8N1.
A reset button is accessble through a hole in the front panel
At the time of this commit, all ethernet ports work under OpenWRT,
including the various NBaseT modes, however the 10GBit SFP+ slot is not
supported.
Installation
--------------
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* Navigate to 'Management' in the OEM web interface and click on 'Firmware upgrade'
to the left.
* Upload the OpenWrt initramfs image, and wait till the switch reboots.
* Connect to the device through serial and change the U-boot boot command.
> fw_setenv bootcmd 'rtk network on; boota'
* Reboot, scp the sysupgrade image to /tmp, verify the checksum and flash it:
> sysupgrade /tmp/openwrt-realtek-rtl930x-zyxel_xgs1250-12-squashfs-sysupgrade.bin
* Upon reboot, you have a functional OpenWrt installation. Leave the bootcmd
value as is - without 'rtk network on' the switch will fail to initialise
the network.
Web recovery
------------
The XGS1250-12 has a handy web recovery that will load when U-boot does
not find a bootable kernel. In case you would like to trigger the web
recovery manually, partially overwrite the firmware partition with some
zeroes:
# dd if=/dev/zero of=/dev/mtd5 bs=1M count=2
If you have serial connected you'll see U-boot will start the web recovery
and print it's listening on 192.168.1.1, but by default it seems to be on
the OEM default IP for the switch - 192.168.1.3. The web recovery only
listens on HTTP (80) and *not* on 443 (HTTPS) unlike the web UI.
Return to stock
---------------
You can flash the ZyXEL firmware images to return to stock:
# sysupgrade -F -n XGS1250-12_Firmware_V1.00(ABWE.1)C0.bix
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Adds configuration routines for the internal SerDes of the
RTL930X and RTL931X.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Adds a rtl931x_phylink_mac_config for the RTL931X and improve
the handling of the RTL930X phylink configuration. Add separate
handling of the RTL839x since some configurations are different
from the RTL838X.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We were using the PHY-ids (the reg entries in the PHY
sections of the .dts) as the port numbers. Now scan the
ports section in the .dts, and use the actual port numbers,
following the phy-handle to the PHY properties.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
When a port is brought up, read the SDS-id via the phy_device
for a given port and use this to configure the SDS when it
is brought up.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL839X does not have an internal phy and thus does not need to have any
firmware as part of the kernel, especially not firmware for the RTL838X.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Selects the new CEVT timer for Realtek instead of the previous
timer driver. While we are at it, we explicitily state we do
not use the I2C driver of the RTL9300.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL9300 has a broken R4K MIPS timer interrupt, however, the
R4K clocksource works. We replace the RTL9300 timer with a
Clock Event Timer (CEVT), which is VSMP aware and can be instantiated
as part of brining a VSMTP cpu up instead of the R4K CEVT source.
For this we place the RTL9300 CEVT timer in arch/mips/kernel
together with other MIPS CEVT timers, initialize the SoC IRQs
from a modified smp-mt.c and instantiate each timer as part
of the MIPS time setup in arch/mips/include/asm/time.h instead
of the R4K CEVT, similarly as is done by other MIPS CEVT timers.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Various fixes to enable Ethernet on the RTL931X:
- Network start and stop sequence for RTL931X HW
- MDIO access on RTL931X SoC
- Chip initialization
- SerDes setup
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Do not lock the register structure in IRQ context. It is not
necessary and leads to lockups under SMP load.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Rename the SoC-specific rtl838x_reg structure in the Ethernet
driver to avoid confusion with the structure of the same name
in the DSA driver. New name is: rtl838x_eth_reg
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Setting bits 20 and 23 in a u16 is obviously wrong.
According to https://www.svanheule.net/realtek/cypress/cputag
cpu_tag[2] starts at bit 48 in the cpu-tag structure, so
bit 43 is bit 5 in cpu_tag[2] and bit 40 is bit 8 in
cpu_tag[2].
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Set CONFIG_FORCE_MAX_ZONEORDER setting to 13 to allow larger
contiguous memory allocation for the DMA of the Ethernet
driver. Increase the number of entries in the RX ring
to 300 making use of the larger DMA region now possible for
receiveing packets.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The GS1900-48 is a 48 + 2 port Gigabit L2 switch with 48 gigabit ports.
Hardware:
RTL8393M SoC
Macronix MX25l12805D (16MB flash)
128MB RAM
6 * RTL8218B external PHY
2 * RTL8231 GPIO extenders to control the port LEDs, system LED and
Reset button
2 Uplink ports are SFP cages which support 1000 Base-X mini GBIC modules.
Power is supplied via a 230 volt mains connector.
The board has a hard reset switch SW1, which is is not reachable from the outside.
J4 provides a 12V RS232 serial connector which is connected through U8 to
the 3.3V UART of the RTL8393. Conversion is done by U8, a SIPEX 3232EC.
To connect to the UART, wires can be soldered to R603 (TX) and R602 (RX).
Installation:
Install the squashfs image via Realtek's original Web-Interface.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Update the IRQ configuration to work with the new rtl-intc controller.
Also change all KSEG1 addresses in reg = <> of the devics to physical
addresses.
Use the new gpio-otto controller instead of the legacy driver.
Also remove the memory node as this is better put into a device .dts.
Also remove the RTL8231 GPIO controller node from this base file
since the chip might not be found in all Realtek RTL839x devices.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Replace the interrupt controller node with the new realtek,rtl-intc
node and change all device interrupts to use the 2 field notation:
interrupts = <[SoC IRQ] [Index to MIPS IRQ]>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
In order to support VSMP, enable support for both VPEs
of the RTL839X and RTL930X SoCs in the irq-realtek-rtl
driver. Add support for IRQ affinity setting.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
In order for the Platform includes to be available on
all sub-targets, make them dependent on CONFIG_RTL83XX.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL838X SoCs do not use Aquantia PHYs, remove this.
Also the RTL838X uses a high resolution R4K timer.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Creates RTL83XX as a basic kernel config parameter for the
RTL838X, RTL839x, RTL930X and RTL931X platforms with respective
configurations for the SoCs, which are introduced in addition.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Create the RTL838x specific Makefiles. Move CPU-type into
rtl838x.mk as this is specifc to that platform. Add
rtl838x subtarget into main Makefile.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
mv generic/target.mk to rtl838x/target.mk in order to create
an initial makefile for the rtl838x sub-architecture
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The EEPROMs on SFP modules are compatible both to I2C as well
as SMBus. However, the kernel so far only supports I2C
access. We add SMBus access routines, because the I2C driver
for the RTL9300 HW only supports that protocol. At the same
time we disable I2C access to PHYs on SFP modules as otherwise
detection of any SFP module would fail. This is not in any
way problematic at this point in time since the RTL93XX
platform so far does not support PHYs on SFP modules.
The patches are copied and rebased version of:
https://bootlin.com/blog/sfp-modules-on-a-board-running-linux/
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL9300/RTL9310 I2C controllers have support for 2 independent I2C
masters, each with a fixed SCL pin, that cannot be changed. Each of these
masters can use 8 (RTL9300) or 16 (RTL9310) different pins for SDA.
This multiplexer directly controls the two masters and their shared
IO configuration registers to allow multiplexing between any of these
busses. The two masters cannot be used in parallel as the multiplex
is protected by a standard multiplex lock.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This adds support for the RTL9300 and RTL9310 I2C controller.
The controller implements the SMBus protocol for SMBus transfers
over an I2C bus. The driver supports selecting one of the 2 possible
SCL pins and any of the 8 possible SDA pins. Bus speeds of
100kHz (standard speed) and 400kHz (high speed I2C) are supported.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This patch removes support for the legacy GPIO driver, since now
the gpio-otto driver can be used on all platforms
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We add support for the RTL930X and RTL931X architectures
in the gpio-realtek-otto.c driver.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Drop patches and files for Linux 5.4 now that we've been using 5.10
for a while and support for Linux 5.4 has gone out-of-sync.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Had to update generic defconfig (make kernel_menuconfig CONFIG_TARGET=generic)
for this bump, but since that only modifies the target defined in .config,
and since that target also needed to be updated for unrelated reasons, manually
propagated the newly added symbol to the generic config.
Removed upstreamed:
pending-5.10/860-Revert-ASoC-mediatek-Check-for-error-clk-pointer.patch[1]
All other patches automatically rebased.
1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.99&id=080f371d984e8039c66db87f3c54804b0d172329
Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200
Signed-off-by: John Audia <graysky@archlinux.us>
All patches automatically rebased.
Build system: x86_64
Build-tested: ramips/mt7621*
*Had to revert 7f1edbd in order to build due to FS#4149
Signed-off-by: John Audia <graysky@archlinux.us>
The GS110TPP has an RGB LED used for system status indication. Expose
all three components as separate GPIO LEDs connected via the device's
RTL8231.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Since the move to 5.10, there are now two GPIO drivers. The gpio0 node
refers to the internal GPIOs, so the indirect-access-bus-id is no longer
relevant for that node.
Set indirect-access-bus-id to the correct value (31) on the correct node
(gpio1) and enable the device.
Cc: Raylynn Knight <rayknight@me.com>
Cc: Michael Mohr <akihana@gmail.com>
Cc: Stijn Segers <foss@volatilesystems.org>
Cc: Stijn Tintel <stijn@linux-ipv6.be>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Bjørn Mork <bjorn@mork.no>
Each of
- CRYPTO_AEAD2
- CRYPTO_AEAD
- CRYPTO_GF128MUL
- CRYPTO_GHASH
- CRYPTO_HASH2
- CRYPTO_HASH
- CRYPTO_MANAGER2
- CRYPTO_MANAGER
- CRYPTO_NULL2
either directly required for mac80211 crypto support, or directly
selected by such options. Support for the mac80211 crypto was enabled in
the generic config since c7182123b9 ("kernel: make cryptoapi support
needed by mac80211 built-in"). So move the above options from the target
configs to the generic config to make it clear why do we need them.
CC: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Both CLANG_VERSION and LLD_VERISON are autogenerated runtime
configuration options, so add them to the kernel configuration filter
and remove from generic and per-target configs to keep configs clean.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Removed target for patch which does not exist:
bcm27xx/patches-5.10/950-0249-kbuild-Disable-gcc-plugins.patch
All patches automatically rebased.
Build system: x86_64
Build-tested: bcm2711/RPi4B, ipq806x/R7800*
Run-tested: bcm2711/RPi4B, ipq806x/R7800*
* Had to revert 7f1edbd412 in order to build
(binutils 2.37, https://bugs.openwrt.org/index.php?do=details&task_id=4149)
Signed-off-by: John Audia <graysky@archlinux.us>
Mac adresses are assigned in the order given by the port list. The
interfaces are also brought up in this order. This target supports
devices with up to 52 ports. Sorting these alphabetically is very
confusing, and assigning mac addresses in alphabetic order does not
match stock firmware behaviour.
Suggested-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
The Realtek Otto watchdog timer driver was accepted upstream, and is
queued for 5.17. Update the patch's file name, and replace by the final
version.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The Netgear GS110TPP v1 switch cannot reliably perform cold reboots
using the system's internal reset controller.
On this device, and the other supported Netgear switches, internal GPIO
line 13 is connected to the system's hard reset logic. Expose this GPIO
on all systems to ensure restarts work properly.
Cc: Raylynn Knight <rayknight@me.com>
Cc: Michael Mohr <akihana@gmail.com>
Cc: Stijn Segers <foss@volatilesystems.org>
Cc: Stijn Tintel <stijn@linux-ipv6.be>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Bjørn Mork <bjorn@mork.no>
Add the gpio-restart driver to the realtek build. This way devices,
which cannot reliably perform resets using the SoC's internal reset
logic, can use a GPIO line to drive the SoC's hard reset input.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The internal GPIO controller on RTL838x is also an IRQ controller, which
requires the 'interrupt-controller' and '#interrupts-cells' properties
to be present in the device tree.
Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Some devices are assigned globally unique MAC addresses for all
ports. These are stored by U-Boot in the second U-Boot enviroment
("sysinfo") as a range of start and end address.
Use the full range if provided.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
The default management interface should be easy to find for users
doing "blind" installations without console access. There are
already multiple examples in the forum of advanced early adopters
having problems locating the management interface after installing
OpenWrt.
Requiring tagged VLAN configration to access the initial management
interface creates unnecessary hassle at best. Errors on the other
end are close to impossible to debug without console access, even
for advanced users. Less advanced users might have problems with
the concept of VLAN tagging.
Limiting management access to a single arbitrary port among up to
52 possible LAN ports makes this even more difficult, for no
reason at all. Users might have reasons to use a different port
for management. And they might even have difficulties using the
OpenWrt selected one. The port might be the wrong type for their
management link (e.g copper instead of fibre). Or they might
depend on PoE power from a device which they can't reconfigure.
User expectations will be based on
- OpenWrt defaults for other devices
- stock firmware default for the device in question
- common default behaviour of similar devices
All 3 cases point to a static IP address accessible on the native
VLAN of any LAN port. A switch does not have any WAN port. All
ports are LAN ports.
This changes the default network configuration in line with these
expectations.
Cc: John Crispin <john@phrozen.org>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
All patches automatically rebased.
Build system: x86_64
Build-tested: ramips/mt7621*
*I am hit with the binutils 2.37 bug so I had to revert 7f1edbd412
in order to downgrade to 2.35.1
Signed-off-by: John Audia <graysky@archlinux.us>
By dropping _machine_restart, users can provide more reliable or
device-specific restart modes.
_machine_halt was already removed in commit f4b687d1f0 ("realtek: use
kernel defined halt"), but quietly reintroduced in commit 8faffa00cb
("realtek: add support for the RTL9300 timer"). Let's remove it again.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Add and enable the Realtek Otto WDT peripheral found on these SoCs.
Default all devices to use standard (cold) reboot and "soc" resets.
Devices that require the PLL value fixup before restarting, should pick
the "cpu" or "software" reset mode. These devices also need to provide a
custom reboot mode, by adding the reboot argument to the kernel command
line:
WDT reset mode | kernel reboot mode
----------------+---------------------------------------
soc | reboot=cold (default if not specified)
cpu | reboot=warm
software | reboot=software
Preferrably, these devices should use an alternative restart method like
gpio-restart to provide reliable restarts.
Note that watchdog restarts are not yet exposed, since the
_machine_restart override is still present.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Add patch submitted upstream to linux-watchdog and replace the MIPS
architecture symbols. Requires one extra patch for the DIV_ROUND_*
macros, which have moved to a different header since 5.10.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
The CPU peripherals on RTL83xx/RTL930x are connected to the CPU via the
Lexra bus. This bus can provide a clock signal to these peripherals, but
no clock driver is currently available. Instead, use a fixed-clock to
provide the clock frequency, and update the dependent peripherals.
Lexra bus clock frequencies:
- RTL838x: 200MHz
- RTL839x: 200MHz
- RTL930x: 175MHz
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
All current devices use identical bootargs, so let's move that to the
common devicetree includes.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Recent versions of Realtek's SDK reset both the ethernet NIC and queues
(SW_NIC_RST and SW_Q_RST bits) when initialising the hardware.
Furthermore, when issuing a CPU reset on the Zyxel GS1900-8 (not
supported by any current driver), the networking part of the SoC is not
reset. This leads to unresponsive network after the restart. By
resetting both the ethernet NIC and queues, networking always comes up
reliably.
Suggested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Backport the patch queued upstream for 5.16. The patch differs slightly
from the upstream patch due to an upstream change that added a
convenience function.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Deleted (upstreamed):
bcm27xx/patches-5.10/950-0145-xhci-add-quirk-for-host-controllers-that-don-t-updat.patch [1]
Manually rebased:
bcm27xx/patches-5.10/950-0355-xhci-quirks-add-link-TRB-quirk-for-VL805.patch
bcm53xx/patches-5.10/180-usb-xhci-add-support-for-performing-fake-doorbell.patch
Note: although automatically rebaseable, the last patch has been edited to avoid
conflicting bit definitions.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.10.y&id=b6f32897af190d4716412e156ee0abcc16e4f1e5
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
Commit 03e1d93e07 ("realtek: add driver support for routing
offload") added routing offload for IPv4, but broke IPv6 routing
completely. The routing table is empty and cannot be updated:
root@gs1900-10hp:~# ip -6 route
root@gs1900-10hp:~# ip -6 route add unreachable default
RTNETLINK answers: Invalid argument
As a side effect, this breaks opkg on IPv4 only systems too,
since uclient-fetch fails when there are no IPv6 routes:
root@gs1900-10hp:~# uclient-fetch http://192.168.99.1
Downloading 'http://192.168.99.1'
Failed to send request: Operation not permitted
Fix by returning NOTIFY_DONE when offloading is unsupported, falling
back to default behaviour.
Fixes: 03e1d93e07 ("realtek: add driver support for routing offload")
Signed-off-by: Bjørn Mork <bjorn@mork.no>
The current rule produces empty trailers, causing the OEM firmware
update application to reject our images.
The double expansion of a makefile variable does not work inside
shell code. The second round is interpreted as a shell expansion,
attempting to run the command ZYXEL_VERS instead of expanding the
$(ZYXEL_VERS) makefile variable.
Fix by removing one level of variable indirection.
Fixes: c6c8d597e1 ("realtek: Add generic zyxel_gs1900 image definition")
Tested-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
The otto GPIO driver does not work with rtl9300 SoCs. Add
the legacy driver again and use that by default in the 9300 .dtsi
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
RTL8393 SoCs older than Revision C hang on accesses to PHYs with PHY address
larger or equal to the CPU-port (52). This will make scanning the MDIO bus
hang forever. Since the RTL8390 platform does not support more than
52 PHYs, return -EIO for phy addresses >= 52. Note that the RTL8390 family
of SoCs has a fixed mapping between port number and PHY-address.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Adds SoC specific routing offload implementations for
RTL8380/90 and RTL9300. RTL83xx supports merely nexthop
routing, RTL9300 full host and prefix routes.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Add generic support for listening to FIB and Event notifier updates and
use this information to hook into the L3 hardware capabilities of the
RTL SoCs.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The ingress filter registers use 2 bits for each port to define the filtering
state, whereas the egress filter uses 1 bit. So for for the ingress filter
the register offset for a given port is:
(port >> 4) << 4: since there are 16 entries in a register of 32 bits
and for the egress filter:
(port >> 5) << 4: since there are 32 entries in a register of 32 bits
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Configure a sane L2 learning configuration upon DSA driver load so that the
switch can start learning L2 addresses. Also configure the correct flood masks
for broadcast and unknown unicast traffice.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This adds RTL93xx-specific MAC configuration routines that allow also configuration
of 10GBit links for phylink. There is support for the Realtek-specific HISGMI
protocol.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This adds support for offloading TC flower by using the Packet Inspection Engine
of the RTL-SoCs. Basic infrastructure support is provide with callbacks to the
tc subsystem and support for HW packet counters.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
All RTL SoCs addresss PHYs via their port number, which is mapped to an
SMI address. Add support for configuring this mapping via the .dts on all
SoCs apart from the 839x, where the mapping to the 64 ports is fixed.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
On RTL83xx enable learning of the MAC source address of the CPU port
from outgoing packets. Add documentation on bit fields. On RTL93xx
enable port-mask usage and the use of internal priority, these
SoCs automatically learn the MAC.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Remove the storm control and attack warnings from the IRQ handler
of the Ethernet driver. There was no consequence to the detection
and the kernel can also handle at least the attacks itself.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This enlarges the size of the TX ring buffer, which prevents warnings
when the buffer runs out of space.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The bootloader can leave the GPIO expander in a state which doesn't have
output drivers enabled so GPIOs will properly work for input but output
operations will have no effect.
To avoid disrupting the boot in case the bootloader left direction and
data registers in an inconsistent state (e.g. pulling SoC's reset to 0)
reconfigure everything as input.
Reviewed-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
This patch adds "KERNEL_TESTING_PATCHVER:=5.10" to the Makefile in
realtek target to allow using Kernel 5.10 for testing.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
On the devices with PoE support, the secondary UART (uart1) on the SoC
is used to communicate between the SoC and controller.
Enable the secondary UART on the following devices:
- D-Link DGS-1210-10P
- Netgear GS110TPP v1
- Netgear GS310TP v1
- ZyXEL GS1900-8HP v1/v2
- ZyXEL GS1900-10HP
- ZyXEL GS1900-24HP v2
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The new backported GPIO driver supports interrupt, so use gpio-keys
instead of gpio-keys-polled for keys connected to the internal GPIO
controller.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
this patch includes the following changes:
- adjust mapping for the new driver
- GPIO 24 -> GPIO 0
- GPIO 47 -> GPIO 0 (+ disabling system LED)
- disable pins in the invalid range
(out of the range 0-31 of the new driver)
- are these pins on the external RTL8231 (&gpio1)?
- GPIO 67 (-> GPIO 3 on &gpio1?)
- GPIO 94 (-> GPIO 30 on &gpio1?)
- drop "indirect-access-bus-id" property from gpio0 node in device dts
files
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
dsa_to_port function in 5.10 returns dsa_port from the port list in
dsa_switch_tree, but the tree is built when the switch is registered
by dsa_register_switch and it's null in rtl83xx_mdio_probe.
So, we need to use dsa_to_port after the registration of the switch.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
This patch adds a pinctrl-single pinmux node to allow disabling system
LED and enabling GPIO 0 (old driver: GPIO 24).
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
this patch fixes the following errors when compiling:
- dsa_switch_alloc is removed[1]
- a parameter "enum dsa_tag_protocol mprot" is added to dsa_tag_protocol
in dsa_switch_ops (include/net/dsa.h)
- several paramters are added to "phylink_mac_link_up" in dsa_switch_ops
(include/net/dsa.h)
added:
- int speed
- int duplex
- bool tx_pause
- bool rx_pause
- a parameter "struct switchdev_trans *trans" is added to
port_vlan_filtering in dsa_switch_ops (include/net/dsa.h)
[1]: https://lore.kernel.org/lkml/20191020031941.3805884-17-vivien.didelot@gmail.com/
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
this patch fixes the following errors when compiling:
- "unsigned int txqueue" is added as an additional parameter of
ndo_tx_timeout in net_device_ops (include/linux/netdevice.h)
- "mac_link_state" in phylink_mac_ops (include/linux/phylink.h)
is renamed to "mac_pcs_get_state" and changed the return value
to void from int
- several parameters are added to "mac_link_up" in phylink_mac_ops
(include/linux/phylink.h) and the order of the parameters is
changed
added:
- int speed
- int duplex
- bool tx_pause
- bool rx_pause
- a parameter "phy_interface_t *interface" is added to of_get_phy_mode
(drivers/of/of_net.c) and returns the state instead of phy mode
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
this patch updates SoC dtsi (rtl838x.dtsi, rtl930x.dtsi) for the
following backported drivers:
- gpio-realtek-otto (5.13)
- spi-realtek-rtl (5.12)
- irq-realtek-rtl (5.12)
And, disable SoC GPIO node (gpio0) in rtl930x.dtsi in dts-5.10.
Currently, the upstreamed driver doesn't support the GPIO controller on
RTL930x SoC.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
the following changes are included in this patch:
- node is enabled by default, drop 'status = "okay"'
- adjust order of "compatible" lines and "reg" lines
- add a new blank line before fixed-link node in rtl830x.dtsi
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
This patch adds "dts-5.10" directory to use backported drivers.
There are several specification changes in the new drivers, so there
are some compatibility issues in using dts/dtsi files for 5.4.
The old DTS files are moved to "dts-5.4", so their corresponding
kernel version is obvious as well.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[change "dts" to "dts-5.4", adjust Makefile]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
The following line is already defined in arch/mips/Kbuild.platforms by
300-mips-add-rtl838x-platform.patch.
platform-$(CONFIG_RTL838X) += rtl838x/
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
A macro with the same name is provided in asm/pgtable.h in Kernel 5.10,
use it and drop from ioremap.h.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
This patch backports "irq-realtek-rtl" driver to Kernel 5.10 from 5.12.
"MACH_REALTEK_RTL" is used as a platform name in upstream, but "RTL838X"
is used in OpenWrt, so update the dependency by the additional patch.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
To use backported irq driver, drop old irq driver from realtek target
and call irqchip_init() in setup.c.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
To backport the upstreamed driver (gpio-realtek-otto) from 5.13, drop the
old driver from realtek target.
And, modify 301-gpio-add-rtl838x-driver.patch to remove rtl838x GPIO
support and rename it only for rtl8231 GPIO support.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
This patch backports "spi-realtek-rtl" driver to Kernel 5.10 from 5.12.
"MACH_REALTEK_RTL" is used as a platform name in upstream, but "RTL838X"
is used in OpenWrt, so update the dependency by the additional patch.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
To backport the upstreamed driver (spi-realtek-rtl) from 5.12, drop the
old driver from realtek target.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
this patch copies the following files from 5.4 to 5.10:
- config-5.4 -> config-5.10
- files-5.4/ -> files-5.10/
- patches-5.4/ -> patches-5.10/
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[rebase on change in files-5.4]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
GPIOs > 31 require special handling. This patch fixes both the
initialisation and direction get/set operations.
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Sander Vanheule <sander@svanheule.net>
The ZyXEL GS1900-24HPv2 is a 24 port PoE switch with two SFP ports, similar to the other GS1900 switches.
Specifications
--------------
* Device: ZyXEL GS1900-24HPv2
* SoC: Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash: 16 MiB
* RAM: W631GG8MB-12 128 MiB DDR3 SDRAM
(stock firmware is configured to use only 64 MiB)
* Ethernet: 24x 10/100/1000 Mbps, 2x SFP 100/1000 Mbps
* LEDs: 1 PWR LED (green, not configurable)
1 SYS LED (green, configurable)
24 ethernet port link/activity LEDs (green, SoC controlled)
24 ethernet port PoE status LEDs
2 SFP status/activity LEDs (green, SoC controlled)
* Buttons: 1 "RESTORE" button on front panel
1 "RESET" button on front panel
* Power 120-240V AC C13
* UART: 1 serial header (J41) with populated standard pin connector on
the left edge of the PCB, angled towards the side.
The casing has a rectangular cutout on the side that provides
external access to these pins.
Pinout (front to back):
+ GND
+ TX
+ RX
+ VCC
Serial connection parameters for both devices: 115200 8N1.
Installation
------------
OEM upgrade method:
(Possible on master once https://patchwork.ozlabs.org/project/openwrt/patch/20210624210408.19248-1-bjorn@mork.no/ is merged)
* Log in to OEM management web interface
* Navigate to Maintenance > Firmware > Management
* If "Active Image" has the first option selected, OpenWrt will need to be
flashed to the "Active" partition. If the second option is selected,
OpenWrt will need to be flashed to the "Backup" partition.
* Navigate to Maintenance > Firmware > Upload
* Upload the openwrt-realtek-generic-zyxel_gs1900-24hp-v2-initramfs-kernel.bin
file by your preferred method to the previously determined partition.
When prompted, select to boot from the newly flashed image, and reboot the switch.
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
> sysupgrade -n /tmp/openwrt-realtek-generic-zyxel_gs1900-24hp-v2-squashfs-sysupgrade.bin
it may be necessary to restart the network (/etc/init.d/network restart) on
the running initramfs image.
U-Boot TFTP method:
* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).
* Set up a TFTP server on your client and make it serve the initramfs image.
* Connect serial, power up the switch, interrupt U-boot by hitting the
space bar, and enable the network:
> rtk network on
* Since the GS1900-24HPv2 is a dual-partition device, you want to keep the OEM
firmware on the backup partition for the time being. OpenWrt can only boot
from the first partition anyway (hardcoded in the DTS). To make sure we are
manipulating the first partition, issue the following commands:
> setsys bootpartition 0
> savesys
* Download the image onto the device and boot from it:
> tftpboot 0x84f00000 192.168.1.10:openwrt-realtek-generic-zyxel_gs1900-24hp-v2-initramfs-kernel.bin
> bootm
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
> sysupgrade -n /tmp/openwrt-realtek-generic-zyxel_gs1900-24hp-v2-squashfs-sysupgrade.bin
it may be necessary to restart the network (/etc/init.d/network restart) on
the running initramfs image.
Signed-off-by: Soma Zambelly <zambelly.soma@gmail.com>
