Some of devices in this target have only 8 MiB space and are closing to
borders of usable space. Particularly, TP-Link RE305 v1 already suffers
from this issue[1], where with current partition layout, on release
images, there's not enough space for overlay. So activate small_flash
feature, which will remove some userspace hardening but will gain almost
1 MiB additional flash memory space. Here is small size comparison of
similar device (RE365 v1) with default config + LuCI:
kernel rootfs sysupgrade
current: 2305728 3635044 5964584
small_flash: 1713571 3320132 5047080
1. https://github.com/openwrt/openwrt/issues/14215
Suggested-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
-+-------------------------+-
| Model | NIC |
-+-------------------------+-
| All | MT7603 + MT7615 |
-+-------------------------+-
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Some MT7915 calibration data consists of two parts. The first part
"eeprom" size is 0xe00. The second part "precal" size is 0x19c10.
Though some devices may not have precal data, it's better to assume
that precal data exists as no users/developers confirm it. On the
other hand, some devices definitely do not contain precal data
because the EEPROM partition size is smaller than the precal NVMEM
cell size.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
TP-Link RE365 is a wireless range extender, hardware-wise resembles
RE305 with slight changes regarding buttons and LEDs.
Specification
SoC: MediaTek MT7628AN
RAM: 64 MiB DDR2
Flash: 8 MiB SPI NOR
WiFi: 2.4 GHz 2T2R integrated
5 GHz 2T2R MediaTek MT7612EN conncted to PCIe lanes
Ethernet: 1x 10/100 Mbps integrated
LEDs: 6x GPIO controlled
Buttons: 4x GPIO controlled
UART: row of 4 holes marked on PCB as J1, starting count from white
triangle
1. VCC (3.3V), 2. GND, 3. RX, 4. TX
baud: 57600, parity: none, flow control: none
Installation
1. Open web management interface.
2. Go to Settings > System Tools > Firmware upgrade.
3. Select "Browse" and select the OpenWrt image with factory.bin suffix.
4. After selecting "Upgrade" firmware writing process will start.
5. Wait till device reboots, power LED should stay solid when it's fully
booted, then it's ready for configuration through LAN port.
Additional information
With how device manufacturer patrtitioned the flash memory, it's possible
that with default packages set, initial factory.bin image won't be
created. In such case, try to reduce packages amount or use older release
for initial conversion to OpenWrt. Later You can use sysupgrade.bin
image with full set of packages because OpenWrt uses unpartitioned flash
memory space unused by vendor firmware.
Reverting to vendor firmware involves converting firmware using
tplink-safeloader with -z option (can be found in ImageBuilder or SDK)
and forcibly applying converted firmware as sysupgrade.
Known issues
WARNING: after removing casing of the device one is exposed to high
voltage and is in a risk of being electrocuted.
Caution when interfacing whith bootloader, saving its environment either
by issuing "saveenv" or selecting option "1: Load system code to SDRAM
via TFTP." in boot menu, any of those will lead to overwriting part of
kernel. This will lead to need of firmware recovery. The cause of this
issue is bootloader having environment offset on flash at 0x40000,
while kernel starts from 0x20000.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
[Wrap long line in DTS]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
This commit:
1. Removes deprecated "label" property from the dts leds subnnodes;
2. Updates buttons and leds dts description according to kernel docs
examples.
Scope: devices well known to me.
Run-tested: TP-Link ec330-g5u, WiFire S1500.nbn
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
MT7688 devices use the "mt7628an.dtsi" as the template. And RT3052
devices use the "rt3050.dtsi" as template. Therefore, we need to add
the corresponding system controller compatible strings to make them
work properly.
Fixes: 1f818b09f8 ("ramips: add proper system clock and reset driver support for legacy SoCs")
Fixes: #14305
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Use reset controller to reset mt7620 ethernet phy instead of directly
writing system control registers. The reset line of "ephy" is 24, so
the DTS resets properties have been updated to get the correct reset
signal.
Tested on HiWiFi HC5861.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Use reset controller to reset mt7620 frame engine instead of directly
writing system control registers.
Tested on HiWiFi HC5861.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Flash: 16MB SPI NOR flash (Macronix MX25L12805D)
Based on the manufactured datasheet this chip is capable of 50MHz.
We dont enable fast-read as mt7621 are only capable of 44mhz in a read state.
Tested on this unit without any issues.
Signed-off-by: David Bentham <db260179@gmail.com>
The rt305x series SOC have two UART devices,
and the one at bus address 0x500 is disabled by default.
Some boards do not even have a pinout for the first one,
so use the same one that the kernel uses at 0xc00 instead.
This allows the lzma-loader printing to be visible
alongside the kernel log in the same console.
Tested-by: Lech Perczak <lech.perczak@gmail.com> # zte,mf283plus
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Before this was reworked, in the file for mt7621 subtarget
(target/linux/ramips/image/lzma-loader/src/board-mt7621.c)
the "Transmitter shift register empty" bit TEMT was used instead of
the "Transmitter holding register empty" bit THRE,
but after the rework, this value was labeled as the THRE bit instead.
Functionally there is no difference, but this is confusing to read,
as it suggests that the subtargets have different bits for the same
register in UART when in reality they are exactly the same.
One can use either bit, or both, at user's descretion
in order to determine whether the UART TX buffer is ready.
The generic kernel early-printk uses both,
(arch/mips/kernel/early_printk_8250.c)
while the ralink-specific early-printk uses only THRE,
(arch/mips/ralink/early_printk.c).
Define both bits and rewrite macros for readability,
keep the same values, as changing which to use should be tested first.
Ref: c31319b66 ("ramips: lzma-loader: Refactor loader")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
The native bus address for UART was entered for rt305x UART_BASE,
but the bootloaders have memory space remapped with the same
virtual memory map the kernel uses for program addressing at boot time.
In UBoot, the remapped address is often defined as TEXT_BASE.
In the kernel, for rt305x this remapped address is RT305X_SYSC_BASE.
(arch/mips/include/asm/mach-ralink/rt305x.h)
Because the ralink I/O busses begin at a low address of 0x10000000,
they are remapped using KSEG0 or KSEG1, which for all 32-bit MIPS SOCs
(arch/mips/include/asm/addrspace.h)
are offsets of 0x80000000 and 0xa0000000 respectively.
This is consistent with the other UART_BASE macros here
and with MIPS memory map documentation.
Before the recent rework of the lzma-loader for ramips,
the original board-$(PLATFORM).c files also did not
use KSEG1ADDR for UART_BASE despite being defined,
which made this mistake easier to occur.
Fix this by defining KSEG1ADDR again and actually use it.
Copy and paste from the kernel's macros for consistency.
Link: https://training.mips.com/basic_mips/PDF/Memory_Map.pdf
Fixes: c31319b66 ("ramips: lzma-loader: Refactor loader")
Reported-by: Lech Perczak <lech.perczak@gmail.com>
Signed-off-by: Michael Pratt <mcpratt@pm.me>
The ESW core needs to be reset together with FE core, so after the
relevant reset controller lines are moved under FE, drop rst_esw and all
related code, which would not execute anyway, because rst_esw would be
NULL. While at that, ensure that if reset line for EPHY cannot be
claimed, a proper error message is reported.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Co-developed-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Split out of the bigger commit, provide commit mesage, refactor error
handling]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Provide commit description, split into logical changes]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.
Fixes: #9284
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Provide commit description, split into logical changes]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Enabling the FE core too early causes the system to hang during boot
uncondtionally, after the reset is released. Increate it to 1-1.2ms
range.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Split previous commit, provide rationale]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Use devm_reset_control_array_get_exclusive to register multiple
reset lines in FE driver. This is required to reattach ESW reset to FE
driver again, based on device tree bindings.
While at that, remove unused fe_priv.rst_ppe field, and add error
message if getting the reset fails.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Co-developed-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Split out of the bigger commit, provide commit mesage, refactor error
handling]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
MT7621 gets a new PCIe driver in the 5.15+ kernel. Allocating wrong PCIe
port will cause the PCIe NIC to not work properly. This commit fixes
the wrong port numbers on Unielec u7621-01.
According to the bootlog, MT7612E (5 GHz) is connected to pcie2, and
MT7603E (2 GHz) is connected to pcie1:
[ 1.294844] mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
[ 1.308635] mt7621-pci 1e140000.pcie: PCIE1 enabled
[ 1.318277] mt7621-pci 1e140000.pcie: PCIE2 enabled
Also correct the led activity for the MT7603e - not used on the MT7612e
Signed-off-by: David Bentham <db260179@gmail.com>
This node is useless because MT7621 uses the generic mips systick
driver instead of the ralink systick driver.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Refresh ramips patches which got out of sync due to backported changes
of the MediaTek Ethernet driver.
Fixes: 6407ef8d2b ("kernel: backport upstream mediatek WED changes")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Seems to be very similar to: https://openwrt.org/toh/tp-link/tl-wr902ac_v3
1 x usb
1 x eth
Powered by mini usb port.
Installation:
Can use TFTP method to install:
1. establish TFTP server at 192.168.0.66
2. provide tp_recover.bin file to the TFTP server
3. turn on router with reset button pressed
4. wait for led blinking, then release reset
Specification based on dmesg from already flashed device:
SoC Type: MediaTek MT7628AN ver:1 eco:2
CPU0 revision is: 00019655 (MIPS 24KEc)
Memory: 56028K/65536K available
CPU Clock: 580MHz
WiFi: MT7613BE
MAC addresses are all the same, except wifi5g which last part is decrement by one, ie.:
eth0 40:ed:00:cf:b9:9b
br-lan 40:ed:00:cf:b9:9b
phy0-ap0 40:ed:00:cf:b9:9b
phy1-ap0 40:ed:00:cf:b9:9a
Signed-off-by: Kamil Jońca <kjonca@onet.pl>
Rostelecom RT-FE-1A is a wireless WiFi 5 router manufactured by Sercomm
company.
Device specification
--------------------
SoC Type: MediaTek MT7621AT
RAM: 256 MiB
Flash: 128 MiB
Wireless 2.4 GHz (MT7603EN): b/g/n, 2x2
Wireless 5 GHz (MT7615E): a/n/ac, 4x4
Ethernet: 5x GbE (WAN, LAN1, LAN2, LAN3, LAN4)
USB ports: No
Button: 2 buttons (Reset & WPS)
LEDs:
- 1x Power (green, unmanaged)
- 1x Status (green, gpio)
- 1x 2.4G (green, hardware, mt76-phy0)
- 1x 2.4G (blue, gpio)
- 1x 5G (green, hardware, mt76-phy1)
- 1x 5G (blue, gpio)
- 5x Ethernet (green, hardware, 4x LAN & WAN)
Power: 12 VDC, 1.5 A
Connector type: barrel
Bootloader: U-Boot
Installation
-----------------
1. Login to the router web interface (default http://192.168.0.1/)
under "admin" account
2. Navigate to Settings -> Configuration -> Save to Computer
3. Decode the configuration. For example, using cfgtool.py tool (see
related section):
cfgtool.py -u configurationBackup.cfg
4. Open configurationBackup.xml and find the following block:
<OBJECT name="User." type="object" writable="1" encryption="0" >
<OBJECT name="1." type="object" writable="1" encryption="0" >
<PARAMETER name="Password" type="string" value="<some value>" writable="1" encryption="1" password="1" />
</OBJECT>
5. Replace <some value> by a new superadmin password and add a line
which enabling superadmin login after. For example, the block after
the changes:
<OBJECT name="User." type="object" writable="1" encryption="0" >
<OBJECT name="1." type="object" writable="1" encryption="0" >
<PARAMETER name="Password" type="string" value="s0meP@ss" writable="1" encryption="1" password="1" />
<PARAMETER name="Enable" type="boolean" value="1" writable="1" encryption="0"/>
</OBJECT>
6. Encode the configuration. For example, using cfgtool.py tool:
cfgtool.py -p configurationBackup.xml
7. Upload the changed configuration (configurationBackup_changed.cfg) to
the router
8. Login to the router web interface (superadmin:xxxxxxxxxx, where
xxxxxxxxxx is a new password from the p.5)
9. Enable SSH access to the router (Settings -> Access control -> SSH)
10. Connect to the router using SSH shell using superadmin account
11. Run in SSH shell:
sh
12. Make a mtd backup (optional, see related section)
13. Change bootflag to Sercomm1 and reboot:
printf 1 | dd bs=1 seek=7 count=1 of=/dev/mtdblock3
reboot
14. Login to the router web interface under admin account
15. Remove dots from the OpenWrt factory image filename
16. Update firmware via web using OpenWrt factory image
Revert to stock
---------------
Change bootflag to Sercomm1 in OpenWrt CLI and then reboot:
printf 1 | dd bs=1 seek=7 count=1 of=/dev/mtdblock3
mtd backup
----------
1. Set up a tftp server (e.g. tftpd64 for windows)
2. Connect to a router using SSH shell and run the following commands:
cd /tmp
for i in 0 1 2 3 4 5 6 7 8 9; do nanddump -f mtd$i /dev/mtd$i; \
tftp -l mtd$i -p 192.168.0.2; md5sum mtd$i >> mtd.md5; rm mtd$i; done
tftp -l mtd.md5 -p 192.168.0.2
MAC Addresses
-------------
+-----+------------+---------+
| use | address | example |
+-----+------------+---------+
| LAN | label | f4:*:66 |
| WAN | label + 11 | f4:*:71 |
| 2g | label + 2 | f4:*:68 |
| 5g | label + 3 | f4:*:69 |
+-----+------------+---------+
The label MAC address was found in Factory, 0x21000
cfgtool.py
----------
A tool for decoding and encoding Sercomm configs.
Link: https://github.com/r3d5ky/sercomm_cfg_unpacker
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
Add the make function 'exp_units' for helping evaluate k/m/g size units in
expressions, and use this to consistently replace many ad hoc substitutions
like '$(subst k,* 1024,$(subst m, * 1024k,$(IMAGE_SIZE)))' in makefiles.
Signed-off-by: Tony Ambardar <itugrok@yahoo.com>
This device is very similar, if not identical, to the TP-Link AX23 v1
but is targeted at service providers and features a completely different
flash layout.
Hardware
--------
CPU: MediaTek MT7621 DAT
RAM: 128MB DDR3 (integrated)
FLASH: 16MB SPI-NOR
WiFi: MediaTek MT7905 + MT7975 (2.4 / 5 DBDC) 802.11ax
SERIAL: 115200 8N1
LEDs - (3V3 - GND - RX - TX) - ETH ports
Installation
------------
Flashing is only possible via a serial connection using the sysupgrade
image; the factory image must be signed. You can flash the sysupgrade
image directly through the U-Boot console, or preferably, by booting the
initramfs image and flashing with the sysupgrade command. Follow these
steps for sysupgrade flashing:
1. Establish a UART serial connection.
2. Set up a TFTP server at 192.168.0.2 and copy the initramfs image
there.
3. Power on the device and press any key to interrupt normal boot.
4. Load the initramfs image using tftpboot.
5. Boot with bootm.
6. If you haven't done so already, back up all stock mtd partitions.
7. Copy the sysupgrade image to the router.
8. Flash OpenWrt through either LuCI or the sysupgrade command. Remember
not to attempt saving settings.
Revert to stock firmware
------------------------
Flash stock firmware via OEM web-recovery mode. If you don't have access
to the stock firmware image, you will need to restore the firmware
partition backed up earlier.
Web-Recovery
------------
The router supports an HTTP recovery mode:
1. Turn off the router.
2. Press the reset button and power on the device.
3. When all LEDs start flashing, release reset and quickly press it
again.
The interface is reachable at 192.168.0.1 and supports installation of
the OEM factory image. Note that flashing OpenWrt this way is not
possible, as mentioned above.
Signed-off-by: Darlan Pedro de Campos <darlanpedro@gmail.com>
