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ramips: dts: rt5350: reset FE and ESW cores together

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Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.

This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.

Fixes: #9284
Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
This commit is contained in:
Lech Perczak 2023-12-12 00:25:02 +01:00 committed by Hauke Mehrtens
parent c5a399f372
commit fc92fecfc7
1 changed files with 4 additions and 4 deletions
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8
target/linux/ramips/dts/rt5350.dtsi
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@ -340,8 +340,8 @@
clocks = <&sysc 12>;
resets = <&sysc 21>;
reset-names = "fe";
resets = <&sysc 21>, <&sysc 23>;
reset-names = "fe", "esw";
interrupt-parent = <&cpuintc>;
interrupts = <5>;
@ -353,8 +353,8 @@
compatible = "ralink,rt5350-esw", "ralink,rt3050-esw";
reg = <0x10110000 0x8000>;
resets = <&sysc 23>, <&sysc 24>;
reset-names = "esw", "ephy";
resets = <&sysc 24>;
reset-names = "ephy";
interrupt-parent = <&intc>;
interrupts = <17>;