Without serial or network access the only option for initial
configuration, is a attached display with USB keyboard, but the keyboard
driver needs to be installed first. So enable keyboard driver by default
to avoid this issue.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Because recent changes to procd, last "console" argument was used as
primary argument and causing no terminal to be spawned on serial
interface. So drop the hardcoded consoles in boot script, since dts has
already an alias specified, which lets procd decide where to spawn the
terminal.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
The old overlay remained after upgrades and would cause failure on first
boot after upgrade, in which no new overlay could be created while old
one was unusable.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Hardware specification:
========
SoC: Qualcomm IPQ8072A
Flash: 512MB (Fidelix FMND4G08S3J-ID)
RAM: 1GB (2x Kingston DDR3L D2516ECMDXGJD)
Ethernet: 1x 10/100/1000/2500/5000Mbps (Marvell AQR114C)
Ethernet: 4x 10/100/1000Mbps (Qualcomm QCA8075)
WiFi1: 6GHz ax 4x4 (Qualcomm QCN9024 + Skyworks SKY85784-11) - channels 33-229
WiFi2: 5GHz ax 4x4 (Qualcomm QCN5054 + Skyworks SKY85755-11) - channels 36-177
WiFi3: 2.4GHz ax 4x4 (Qualcomm QCN5024 + Skyworks SKY8340-11)
IoT: Bluetooth 5, Zigbee and Thread (NXP K32W041)
LED: 1x RGB status (NXP PCA9633)
USB: 1x USB 3.0
Button: WPS, Reset
Flash instructions:
========
1. Manually upgrade firmware using openwrt-qualcommax-ipq807x-linksys_mx8500-squashfs-factory.bin image.
More details can be found here: https://www.linksys.com/support-article?articleNum=47547
After first boot check actual partition:
- fw_printenv -n boot_part
and install firmware on second partition using command in case of 2:
- mtd -r -e kernel -n write openwrt-qualcommax-ipq807x-linksys_mx8500-squashfs-factory.bin kernel
and in case of 1:
- mtd -r -e alt_kernel -n write openwrt-qualcommax-ipq807x-linksys_mx8500-squashfs-factory.bin alt_kernel
2. Installation using serial connection from OEM firmware (default login: root, password: admin):
- fw_printenv -n boot_part
In case of 2:
- flash_erase /dev/mtd21 0 0
- nandwrite -p /dev/mtd21 openwrt-qualcommax-ipq807x-linksys_mx8500-squashfs-factory.bin
or in case of 1:
- flash_erase /dev/mtd23 0 0
- nandwrite -p /dev/mtd23 openwrt-qualcommax-ipq807x-linksys_mx8500-squashfs-factory.bin
After first boot install firmware on second partition:
- mtd -r -e kernel -n write openwrt-qualcommax-ipq807x-linksys_mx8500-squashfs-factory.bin kernel
or:
- mtd -r -e alt_kernel -n write openwrt-qualcommax-ipq807x-linksys_mx8500-squashfs-factory.bin alt_kernel
3. Installation from initramfs image using USB drive:
Put the initramfs image on the USB drive:
- dd bs=1M if=openwrt-qualcommax-ipq807x-linksys_mx8500-initramfs-uImage.itb of=/dev/sda
Stop u-boot and run:
- usb start && usbboot $loadaddr 0 && bootm $loadaddr
Write firmware to the flash from initramfs:
- mtd -e kernel -n write openwrt-qualcommax-ipq807x-linksys_mx8500-squashfs-factory.bin kernel
and:
- mtd -r -e alt_kernel -n write openwrt-qualcommax-ipq807x-linksys_mx8500-squashfs-factory.bin alt_kernel
4. Back to the OEM firmware:
- mtd -e kernel -n write FW_MX8500_1.0.11.208937_prod.img kernel
and:
- mtd -r -e alt_kernel -n write FW_MX8500_1.0.11.208937_prod.img alt_kernel
5. USB recovery:
Put the initramfs image on the USB:
- dd bs=1M if=openwrt-qualcommax-ipq807x-linksys_mx8500-initramfs-uImage.itb of=/dev/sda
Set u-boot env:
- fw_setenv bootusb 'usb start && usbboot $loadaddr 0 && bootm $loadaddr'
- fw_setenv bootcmd 'run bootusb; if test $auto_recovery = no; then bootipq; elif test $boot_part = 1; then run bootpart1; else run bootpart2; fi'
AQR firmware:
========
1. Firmware loading:
To properly load the firmware and initialize AQR PHY, we must use the u-boot aq_load_fw function.
To do this, you need to modify u-boot env:
With USB recovery:
- fw_setenv bootcmd 'aq_load_fw; run bootusb; if test $auto_recovery = no; then bootipq; elif test $boot_part = 1; then run bootpart1; else run bootpart2; fi'
and without:
- fw_setenv bootcmd 'aq_load_fw; if test $auto_recovery = no; then bootipq; elif test $boot_part = 1; then run bootpart1; else run bootpart2; fi'
2. Firmware updating:
Newer firmware (AQR-G4_v5.6.5-AQR_WNC_SAQA-L2_GT_ID45287_VER24005.cld) is available in the latest OEM firmware.
To load this firmware via u-boot, we need to add the MBN header and update 0:ethphyfw partition.
For MBN header we can use script from this repository: https://github.com/testuser7/aqr_mbn_tool
- python aqr_mbn_tool.py AQR-G4_v5.6.5-AQR_WNC_SAQA-L2_GT_ID45287_VER24005.cld
To update partition we need to install kmod-mtd-rw package first:
- insmod mtd-rw.ko i_want_a_brick=1
- mtd -e /dev/mtd26 -n write aqr_fw.mbn /dev/mtd26
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/14883
Signed-off-by: Robert Marko <robimarko@gmail.com>
Define common Linksys MX device for MX4200v1/v2 and MX5300.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/14883
Signed-off-by: Robert Marko <robimarko@gmail.com>
Remove gpio16 from the default NAND pinctrl configuration
as its unused and only needed for LCD.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/14883
Signed-off-by: Robert Marko <robimarko@gmail.com>
All three PCIe ports are reported non working on Meraki MR42/MR52 boards
since kernel 6.1 with the issue of PCIe PHY link never coming up thus
no WLAN cards are available on the boards.
After debugging it seems that PCIe worked on 5.15 and older purely by
accident as device DTS was using /delete-property/ perst-gpios; in each
of the 3 PCIe nodes but there was no "perst-gpios" property in the SoC DTSI
as it was still using the older "perst-gpio" property so it was not getting
removed from the device DTS.
However, in kernel 6.1 commit ("ARM: dts: qcom-*: replace deprecated
perst-gpio with perst-gpios") updated all Qualcomm DTS-es to use the newer
"perst-gpios" and thus once ipq806x moved to 6.1 PCIe stopped working as
now that property was being dropped from the device DTS.
So, since the removal of PERST pins seems to have been wrong from the start
lets drop the property removal from MR42/MR52.
Fixes: #15408
Link: https://github.com/openwrt/openwrt/pull/15509
Signed-off-by: Robert Marko <robimarko@gmail.com>
Our kernel export stripping has been broken on 6.6 from the start since
upstream kernel really reworked stuff in ("kbuild: generate KSYMTAB entries
by modpost") and other commits as well.
So, until this is either fixed or reworked lets drop the patch as it doesnt
make sense to carry it knowing its broken and it can always be easily
restored.
Link: https://github.com/openwrt/openwrt/pull/15498
Signed-off-by: Robert Marko <robimarko@gmail.com>
This code assumed that the mt7628an_tplink_8m.dtsi file defines
mediatek,mtd-eeprom for the wmac and sets status to okay.
The mediatek,mtd-eeprom definition was removed in commit e93f41adee
("ramips: convert MT7628 EEPROM to NVMEM format") but the dts for these
two devices was not adapted to include the eeprom position on its own.
The status = "okay" property was removed in 0a1d15642f ("ramips:
mt7628: use nvmem-layout"), but the property was not added to these dts
files.
Without this change wifi does not work for these devices.
Fixes: e93f41adee ("ramips: convert MT7628 EEPROM to NVMEM format")
Fixes: 0a1d15642f ("ramips: mt7628: use nvmem-layout")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Linux kernel commit 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using
gpiod API") not only switched to the gpiod API, but also inverted /
changed the polarity of the GPIO.
According to the PCI specification, the RST# pin is an active-low
signal. However, most of the device trees that have been widely used for
a long time (mainly in the openWrt project) define this GPIO as
active-high and the old driver code inverted the signal internally.
Apparently there are actually boards where the reset gpio must be
operated inverted. For this reason, we cannot use the GPIOD_OUT_LOW/HIGH
flag for initialization. Instead, we must explicitly set the gpio to
value 1 in order to take into account any "GPIO_ACTIVE_LOW" flag that
may have been set.
In order to remain compatible with all these existing device trees, we
should therefore keep the logic as it was before the commit.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
This is required for linux-6.1 compatibility.
IRQs are not automatically mapped from HW to virtual IRQ numbers when
the IRQ domain is registered. This happens when the IRQ number is read
from the device tree based on the IRQ domain from the device tree now.
In kernel 5.15 it was done when the IRQ domain was registered.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
This is required for linux-6.1 compatibility.
IRQs are not automatically mapped from HW to virtual IRQ numbers when
the IRQ domain is registered. This happens when the IRQ number is read
from the device tree based on the IRQ domain from the device tree now.
In kernel 5.15 it was done when the IRQ domain was registered.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
This is required for linux-6.1 compatibility.
IRQs are not automatically mapped from HW to virtual IRQ numbers when
the IRQ domain is registered. This happens when the IRQ number is read
from the device tree based on the IRQ domain from the device tree now.
In kernel 5.15 it was done when the IRQ domain was registered.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Use dev_err_probe() to get rid of the following warning which is
seen when the PCIe PHY has not been probed yet:
pcie-xrx200 1d900000.pcie: failed to get the PCIe PHY
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
This backports some patches for the gswip switch driver.
I copied them from this repository:
https://github.com/xdarklight/linux/commits/lantiq-gswip-integration-20221022
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
[drop some patches which may break functionality at the moment]
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
If the reverted timer driver fails to allocate interrupts handle the
error better.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
[moved printk before the cleanup for-loop]
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Make all the patches apply and delete the ones already integrated into
upstream Linux kernel. This also refreshes some of the kernel
configurations.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
[refreshed for linux 6.1.89]
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
This is an automatically generated commit which aids following Kernel patch
history, as git will see the move and copy as a rename thus defeating the
purpose.
For the original discussion see:
https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
This refreshes the configuration for Linux kernel 5.15.
I first selected the xrx200 subtarget and then refreshed the target
kernel configuration using this command:
make kernel_oldconfig CONFIG_TARGET=target
Then I selected one subtarget after the other and refreshed their
configuration using this command:
make kernel_oldconfig CONFIG_TARGET=subtarget
I compared the kernel configuration used to compile the kernel from the
build directory for each subtarget before and after this task and it was
still the same.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
[refreshed config for linux 5.15.158]
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
There is a custom LED controller between the 3 SoC GPIO outputs and
the red and blue LEDs of the device. It implements a strange mapping
that includes fixed, flashing, and breathing modes.
The current DTS configuration causes OpenWrt to flash the LEDs over
the controller's own flashing, resulting in chaotic output in boot,
failsafe, and upgrade modes.
This change fixes the LEDs in the best way possible as long as each
OpenWrt running state is limited to be signaled by a single led.
Signed-off-by: Rodrigo Balerdi <lanchon@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/15440
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
There is no need to use 'list_for_each_entry_safe' here, as nothing is
removed from the list in the 'for' loop.
Use 'list_for_each_entry' instead, it is slightly less verbose.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://github.com/openwrt/openwrt/pull/15435
Link: https://github.com/openwrt/openwrt/pull/15435
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fixes the issue of RTL8221B-VB-CG not being detected correctly.
Reverts changes from f6c27b2, leaving only the read_c45 test.
Fixed: #15093
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Lets give Linux 6.6 a try.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://github.com/openwrt/openwrt/pull/15416
Signed-off-by: Robert Marko <robimarko@gmail.com>
Refresh kernel config for Linux 6.6.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://github.com/openwrt/openwrt/pull/15416
Signed-off-by: Robert Marko <robimarko@gmail.com>
Refresh the only remaining downstream patch.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://github.com/openwrt/openwrt/pull/15416
Signed-off-by: Robert Marko <robimarko@gmail.com>
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://github.com/openwrt/openwrt/pull/15416
Signed-off-by: Robert Marko <robimarko@gmail.com>
Update default kernel version to 6.6 and drop configs and patches for
kernel 6.1. We can also omit the conditional to include DTS dir.
Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
Link: https://github.com/openwrt/openwrt/pull/15449
Signed-off-by: Robert Marko <robimarko@gmail.com>
Like AVM 1200 these devices also do not use QCA807x PHY at all and thus
they disables all of the individual PHY nodes, however this is not enough
anymore since the conversion to PHY package.
Now its now enough to disable the PHY-s in the package alone, but the PHY
package node itself must also be disabled.
Fixes: 1b931c33a2 ("ipq40xx: adapt to new Upstream QCA807x PHY driver")
Link: https://github.com/openwrt/openwrt/pull/15444
Signed-off-by: Robert Marko <robimarko@gmail.com>
- Soc: MediaTek MT7621AT
- RAM: 512 MB (DDR3)
- Flash: 16 MB (SPI NOR)
- WiFi: MediaTek MT7905DAN, MediaTek MT7975DN
- Ethernet: 1 WAN, 3 LAN (Gigabit)
- Buttons: Reset, Joylink
- LEDs: (red, blue, green), routed to one indicator in the top of the
device
- Power: DC 12V 1A tip positive
- 1 TF Card Slot
The pins for the serial console are already labeled on the board
J4(V, R, T, G). Serial settings: 3.3V, 115200
MAC addresses:
| | MAC | Algorithm |
| ------- | ----------------- | --------- |
| label | dc:d8:xx:xx:xx:01 | label |
| LAN | dc:d8:xx:xx:xx:01 | label |
| WAN | dc:d8:xx:xx:xx:02 | label+1 |
| WLAN 2g | dc:d8:xx:xx:xx:03 | label+2 |
| WLAN 5g | de:d8:xx:xx:xx:04 | label+3 |
1. rename the
openwrt-ramips-mt7621-jdcloud_re-cp-02-squashfs-sysupgrade.bin
to JDCOS.bin
2. start a TFTP server from IP address 192.168.68.10 and serve the
image named JDCOS.bin
3. connect your device to the LAN port
4. power up the router and press any key on the console to interrupt
the boot process.
5. enter the following commands on the router console
1. setenv bootcount 6
2. saveenv
3. reset
> NOTE: wait for the restart, it will automatically fetch the
> image named JDCOS.bin from the TFTP server and write it into
> the flash. After the writing is completed, the router will be
> automatically restarted.
Unable to recognize large-capacity TF card, see #14042. But the patch
https://github.com/openwrt/openwrt/issues/14042#issuecomment-1910769942
works
Co-Authored-By: Jianti Chen <clbcjt@outlook.com>
Signed-off-by: Sheng Huang <shenghuang147@gmail.com>
Hardware:
SoC: MT7981b
RAM: 256 MB
Flash: 128 MB SPI NAND
Ethernet:
1x 2.5Gbps (rtl8221b)
1x 1Gbps (integrated phy)
WiFi: 2x2 MT7981
Buttons: Reset, WPS
LED: 1x multicolor
Solder on UART:
- remove rubber ring on the bottom
- remove screws
- pull up the cylinder, maybe help by push on an ethernet socket with a screwdriver
- remove the (3) screws holding the board in the frame
- remove the board from the frame to get to the screws for the silver, flat heat shield
- remove the (3) screws holding the heat shield
- solder UART pins to the back of the board
- make sure to have the pins point out on side with the black, finned heat spread
- the markings for the pins are going to be below the silver heat shield
- Vcc is not needed
If you don't intend on using the UART outside of the installation process, you might not
want to solder:
- carefully scrape off the thin layer of epoxy on the holes (not the copper)
- place your pin header with the UART attached in the holes
- the pins, starting with the one closest to the socket:
- Vcc (not required)
- GND
- RX
- TX
- either wedge the header or hold it with your fingers so that the pins stay in contact with the board
Installation (UART):
- attach an Ethernet cable to the 1Gbps port (black) on the router
- hold the reset button while powering the router
- press CTRL-C or wait for the timeout to get to the U-Boot prompt
- prepare a TFTP server on the network to supply ..-initramfs-kernel.bin
- use 'tftpboot' in the U-Boot shell to pull the image
- boot the image using 'bootm'
- push the ..-sysupgrade to the router using your preferred method
- perform the upgrade with 'sysupgrade -n'
There is a recovery mechanism that involves fetching a file called 'recovery.bin' but that is not understood yet.
Signed-off-by: Leon M. Busch-George <leon@georgemail.eu>
FCC ID: A8J-EWS660AP
Engenius ENS1750 is an outdoor wireless access point with
2 gigabit ethernet ports, dual-band wireless,
internal antenna plates, and 802.3at PoE+
Engenius EWS660AP, ENS1750, and ENS1200 are "electrically identical,
different model names are for marketing purpose" according to docs
provided by Engenius to the FCC.
**Specification:**
- QCA9558 SOC 2.4 GHz, 3x3
- QCA9880 WLAN mini PCIe card, 5 GHz, 3x3, 26dBm
- AR8035-A PHY RGMII GbE with PoE+ IN
- AR8033 PHY SGMII GbE with PoE+ OUT
- 40 MHz clock
- 16 MB FLASH MX25L12845EMI-10G
- 2x 64 MB RAM
- UART at J1 populated, RX grounded
- 6 internal antenna plates (5 dbi, omni-directional)
- 5 LEDs, 1 button (power, eth0, eth1, 2G, 5G) (reset)
**MAC addresses:**
Base MAC addressed labeled as "MAC"
Only one Vendor MAC address in flash
eth0 *:d4 MAC art 0x0
eth1 *:d5 --- art 0x0 +1
phy1 *:d6 --- art 0x0 +2
phy0 *:d7 --- art 0x0 +3
**Serial Access:**
the RX line on the board for UART is shorted to ground by resistor R176
therefore it must be removed to use the console
but it is not necessary to remove to view boot log
optionally, R175 can be replaced with a solder bridge short
the resistors R175 and R176 are next to the UART RX pin
**Installation:**
2 ways to flash factory.bin from OEM:
Method 1: Firmware upgrade page:
OEM webpage at 192.168.1.1
username and password "admin"
Navigate to "Firmware Upgrade" page from left pane
Click Browse and select the factory.bin image
Upload and verify checksum
Click Continue to confirm and wait 3 minutes
Method 2: Serial to load Failsafe webpage:
After connecting to serial console and rebooting...
Interrupt uboot with any key pressed rapidly
execute `run failsafe_boot` OR `bootm 0x9fd70000`
wait a minute
connect to ethernet and navigate to
"192.168.1.1/index.htm"
Select the factory.bin image and upload
wait about 3 minutes
**Return to OEM:**
If you have a serial cable, see Serial Failsafe instructions
otherwise, uboot-env can be used to make uboot load the failsafe image
ssh into openwrt and run
`fw_setenv rootfs_checksum 0`
reboot, wait 3 minutes
connect to ethernet and navigate to 192.168.1.1/index.htm
select OEM firmware image from Engenius and click upgrade
**TFTP recovery:**
Requires serial console, reset button does nothing
rename initramfs.bin to '0101A8C0.img'
make available on TFTP server at 192.168.1.101
power board, interrupt boot
execute tftpboot and bootm 0x81000000
**Format of OEM firmware image:**
The OEM software of ENS1750 is a heavily modified version
of Openwrt Kamikaze. One of the many modifications
is to the sysupgrade program. Image verification is performed
simply by the successful ungzip and untar of the supplied file
and name check and header verification of the resulting contents.
To form a factory.bin that is accepted by OEM Openwrt build,
the kernel and rootfs must have specific names...
openwrt-ar71xx-generic-ens1750-uImage-lzma.bin
openwrt-ar71xx-generic-ens1750-root.squashfs
and begin with the respective headers (uImage, squashfs).
Then the files must be tarballed and gzipped.
The resulting binary is actually a tar.gz file in disguise.
This can be verified by using binwalk on the OEM firmware images,
ungzipping then untaring.
Newer EnGenius software requires more checks but their script
includes a way to skip them, otherwise the tar must include
a text file with the version and md5sums in a deprecated format.
The OEM upgrade script is at /etc/fwupgrade.sh.
OKLI kernel loader is required because the OEM software
expects the kernel to be no greater than 1536k
and the factory.bin upgrade procedure would otherwise
overwrite part of the kernel when writing rootfs.
Note on PLL-data cells:
The default PLL register values will not work
because of the external AR8035 switch between
the SOC and the ethernet port.
For QCA955x series, the PLL registers for eth0 and eth1
can be see in the DTSI as 0x28 and 0x48 respectively.
Therefore the PLL registers can be read from uboot
for each link speed after attempting tftpboot
or another network action using that link speed
with `md 0x18050028 1` and `md 0x18050048 1`.
The clock delay required for RGMII can be applied
at the PHY side, using the at803x driver `phy-mode`.
Therefore the PLL registers for GMAC0
do not need the bits for delay on the MAC side.
This is possible due to fixes in at803x driver
since Linux 5.1 and 5.3
Tested-by: Kevin Abraham <kevin@westhousefarm.com>
Signed-off-by: Kevin Abraham <kevin@westhousefarm.com>
Add additional PWM fan cooling step and enable fan on BPi-R4.
Suggested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
We should setup the registers for trapping LLDP packets to the CPU.
Currently, these packets are forwarded to all ports which is not desired
behaviour.
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
These registers control the handling of Link Layer Discovery Protocol
(LLDP) packets. This seems to be a typo in the naming.
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
