The way to register the switch MDIO bus and PHYs on the bus in upstream
Linux is more strict and requires each PHY to explicitely state the
interrupt instead of assuming it in case the 'interrupts' property in DT
is missing.
Add missing interrupts for the PHYs of the build-in 4x1GE switch of the
MT7988 SoC.
Fixes: 4354b34f6f ("generic: 6.6: sync mt7530 DSA driver with upstream")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
In commit cd4de3251c ("mediatek: wait for fitblk rootfs"), the linux
6.6 files and patches has been forgotton to be fixed.
Fixes: cd4de3251c ("mediatek: wait for fitblk rootfs")
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Adding the aliases also for Linux 6.6 was forgotten and is required for
U-Boot to hand down persistent MAC addresses to Linux.
Fixes: 5709254690 ("mediatek: bpi-r4: store random MAC addresses for the BPi-R4")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This adds support for the bpi-r4 variant with internal 2.5G PHY and
additional ethernet port instead of second sfp.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Move the common parts of the mt7988a-bananapi-bpi-r4.dts to a dtsi file.
This is done to prepare support for the 2.5G Ethernet Variant.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Use 'mediatek,mt7988a' instead of 'mediatek,mt7988' as compatible
string to be in-sync with upstream and no longer break the cpufreq
driver which was also kept in sync with upstream.
Fixes: 56dd6b473b ("mediatek: sync cpufreq support with changed compatible string")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add missing CLK_TOP_PEXTP_Px_SEL clock for each of the 4 PCIe interfaces
of the MT7988 SoC. Without that clock PCIe doesn't work reliable.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
