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mediatek: mt7988: add missing clock for PCIe ports

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Add missing CLK_TOP_PEXTP_Px_SEL clock for each of the 4 PCIe interfaces
of the MT7988 SoC. Without that clock PCIe doesn't work reliable.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle 2024-03-15 14:07:58 +00:00
parent 904aa43865
commit 2b25f66d0a
2 changed files with 24 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
View File

@ -948,9 +948,10 @@
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
<&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
<&infracfg CLK_INFRA_133M_PCIE_CK_P2>,
<&topckgen CLK_TOP_PEXTP_P2_SEL>;
clock-names = "pl_250m", "tl_26m", "peri_26m",
"top_133m";
"top_133m", "pextp_clk";
pinctrl-names = "default";
pinctrl-0 = <&pcie2_pins>;
phys = <&xphyu3port0 PHY_TYPE_PCIE>;
@ -989,9 +990,10 @@
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
<&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
<&infracfg CLK_INFRA_133M_PCIE_CK_P3>,
<&topckgen CLK_TOP_PEXTP_P3_SEL>;
clock-names = "pl_250m", "tl_26m", "peri_26m",
"top_133m";
"top_133m", "pextp_clk";
pinctrl-names = "default";
pinctrl-0 = <&pcie3_pins>;
#interrupt-cells = <1>;
@ -1028,9 +1030,10 @@
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
<&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
<&infracfg CLK_INFRA_133M_PCIE_CK_P0>,
<&topckgen CLK_TOP_PEXTP_P0_SEL>;
clock-names = "pl_250m", "tl_26m", "peri_26m",
"top_133m";
"top_133m", "pextp_clk";
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
#interrupt-cells = <1>;
@ -1067,9 +1070,10 @@
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
<&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
<&infracfg CLK_INFRA_133M_PCIE_CK_P1>,
<&topckgen CLK_TOP_PEXTP_P1_SEL>;
clock-names = "pl_250m", "tl_26m", "peri_26m",
"top_133m";
"top_133m", "pextp_clk";
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
#interrupt-cells = <1>;

20
target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
View File

@ -948,9 +948,10 @@
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
<&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
<&infracfg CLK_INFRA_133M_PCIE_CK_P2>,
<&topckgen CLK_TOP_PEXTP_P2_SEL>;
clock-names = "pl_250m", "tl_26m", "peri_26m",
"top_133m";
"top_133m", "pextp_clk";
pinctrl-names = "default";
pinctrl-0 = <&pcie2_pins>;
phys = <&xphyu3port0 PHY_TYPE_PCIE>;
@ -989,9 +990,10 @@
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
<&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
<&infracfg CLK_INFRA_133M_PCIE_CK_P3>,
<&topckgen CLK_TOP_PEXTP_P3_SEL>;
clock-names = "pl_250m", "tl_26m", "peri_26m",
"top_133m";
"top_133m", "pextp_clk";
pinctrl-names = "default";
pinctrl-0 = <&pcie3_pins>;
#interrupt-cells = <1>;
@ -1028,9 +1030,10 @@
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
<&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
<&infracfg CLK_INFRA_133M_PCIE_CK_P0>,
<&topckgen CLK_TOP_PEXTP_P0_SEL>;
clock-names = "pl_250m", "tl_26m", "peri_26m",
"top_133m";
"top_133m", "pextp_clk";
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
#interrupt-cells = <1>;
@ -1067,9 +1070,10 @@
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
<&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
<&infracfg CLK_INFRA_133M_PCIE_CK_P1>,
<&topckgen CLK_TOP_PEXTP_P1_SEL>;
clock-names = "pl_250m", "tl_26m", "peri_26m",
"top_133m";
"top_133m", "pextp_clk";
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
#interrupt-cells = <1>;