Priority values passed to the egress (TX) frame header initialiser are
invalid when smaller than 0, and should not be assigned to the frame.
Queue assignment is then left to the switch core logic.
Current code for RTL83xx forces the passed priority value to be
positive, by always masking it to the lower bits, resulting in the
priority always being set and enabled. RTL93xx code doesn't even check
the value and unconditionally assigns the (32 bit) value to the (5 bit)
QID field without masking.
Fix priority assignment by only setting the AS_QID/AS_PRI flag when a
valid value is passed, and properly mask the value to not overflow the
QID/PRI field.
For RTL839x, also assign the priority to the right part of the frame
header. Counting from the leftmost bit, AS_PRI and PRI are in bits 36
and 37-39. The means they should be assigned to the third 16 bit value,
containing bits 32-47.
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The flag to enable L2 address learning on egress frames is in CPU header
bit 40, with bit 0 being the leftmost bit of the header. This
corresponds to BIT(7) in the third 16-bit value of the header.
Correctly set L2LEARNING by fixing the off-by-one error.
Fixes: 9eab76c84e ("realtek: Improve TX CPU-Tag usage")
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The flag to enable the outgoing port mask is in CPU header bit 43, with
bit 0 being the leftmost bit of the header. This corresponds to BIT(4)
in the third 16-bit value of the header.
Correctly set AS_DPM by fixing the off-by-one error.
Fixes: 9eab76c84e ("realtek: Improve TX CPU-Tag usage")
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
setup.c unconditionally sets the sys-led mode (blinking rate) to a
permanent high output. This may cause issues when a board expects this
pin to toggle periodically, e.g. when hooked up to an external watchdog.
If the sys-led peripheral is used to control an LED, the mux should be
configured to use the pin as GPIO0, allowing for better control as a
GPIO LED.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Setting up DSA bond silently fails if mode is not 802.3ad. Add log message
to fix it. As we are already here harmonize all logging messages in the
add/delete functions.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Do not reset the RTL930x SerDes on link changes, instead set up
the SDS with internal PHYs for the SFP+ ports only.
This fixes the 8 1GBit ports on the Zyxel XGS1250 which
do not work without this patch.
A complete SerDes reset was performed on all SerDes links. For copper
1Gbit ports, this is commonly a single XGMII link to an RTL8218D. There
is however no support for setting up the XGMII link on RTL9300/RTL9310,
thereby wiping the (RX/TX) setup done by u-boot and breaking the 1GBit
ports. No SerDes reset should be done for these links.
The handling of SGMII/HiSGMII, 1000BX or 10GR links is actually entirely
different. All these modes need to be suitably RX calibrated and the
pre- main and post- amplifiers set up properly for TX.
The 10GBit SFP+ fiber links are recalibrated instead of reset, which
e.g. is necessary when someone pulls a module out and puts another in.
This makes swapping out 10GBit fiber modules possible. 1GBit modules are
not yet supported, nor any modules with an internal phy.
Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
[rewrite commit message based on discussion]
Link: http://lists.infradead.org/pipermail/openwrt-devel/2022-May/038623.html
Signed-off-by: Sander Vanheule <sander@svanheule.net>
This fixes a bug where frames sent to the switch itself were
flooded to all ports unless the MAC address of the CPU-port
was learned otherwise.
Tested-by: Wenli Looi <wlooi@ucalgary.ca>
Tested-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
[fix code formatting]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The I/O base address for the timers was hardcoded into the driver,
or derived from the HW IRQ number as an even more horrible hack. All
supported SoC families have these timers, but with hardcoded addresses
the code cannot be reused right now.
Request the timer's base address from the DT specification, and store it
in a private struct for future reference.
Matching the second interrupt specifier, the address range for the
second timer is added to the DT specification.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
A Locking bug in the packet receive path was introduced with PR
#4973. The following patch prevents the driver from locking
after a few minutes with an endless flow of
[ 1434.185085] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000f8
[ 1434.208971] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc
[ 1434.794800] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc
[ 1435.049187] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
When initialising the driver, check if the RTL8231 chip is actually
present at the specified address. If the READY_CODE value does not match
the expected value, return -ENXIO to fail probing.
This should help users to figure out which address an RTL8231 is
configured to use, if measuring pull-up/-down resistors is not an
option.
On an unsuccesful probe, the driver will log:
[ 0.795364] Probing RTL8231 GPIOs
[ 0.798978] rtl8231_init called, MDIO bus ID: 30
[ 0.804194] rtl8231-gpio rtl8231-gpio: no device found at bus address 30
When a device is found, only the first two lines will be logged:
[ 0.453698] Probing RTL8231 GPIOs
[ 0.457312] rtl8231_init called, MDIO bus ID: 31
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
The SMI bus ID for RTL8231 currently defaults to 0, and can be
overridden from the devicetree. However, there is no value check on the
DT-provided value, aside from masking which would only cause value
wrap-around.
Change the driver to always require the "indirect-access-bus-id"
property, as there is no real reason to use 0 as default, and perform a
sanity check on the value when probing. This allows the other parts of
the driver to be simplified a bit.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Set the gpio_chip.base to -1 to use automatic GPIO line indexing.
Setting base to 0 or a positive number is deprecated and should not be
used.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
The RTL8231's gpio_chip.ngpio was set to 36, which is the largest valid
GPIO index. Fix the allowed number of GPIOs by setting ngpio to 37, the
actual line count.
Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Replace magic values with more self-descriptive code now that I start
to understand more about the design of the PHY (and MDIO controller).
Remove one line before reading RTL8214FC internal PHY id which turned
out to be a no-op and can hence safely be removed (confirmed by
INAGAKI Hiroshi[1])
[1]: df8e6be59a (r66890713)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Instead of directly calling SoC-specific functions in order to access
(paged) MII registers or MMD registers, create infrastructure to allow
using the generic phy_*, phy_*_paged and phy_*_mmd functions.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* Add missing Clause-45 write support for rtl931x
* Switch to use helper functions in all Clause-45 access functions to
make the code more readable.
* More meaningful/unified debugging output (dynamic kprintf)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Using the led-set attribute of a port in the dts we allow configuration
of the port leds. Each led-set is being defined in the led-set configuration
of the .dts, giving a specific configuration to steer the port LEDs via a serial
connection.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL8221B PHY is a newer version of the RTL8226, also supporting
2.5GBit Ethernet. It is found with RTL931X devices such as the
EdgeCore ECS4125-10P
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Both the Aquantia AQR113c and the RTL8226 PHYs in the Zyxel XGS1250 and the
Zyxel XGS1210 require special polling configuration settings in the
RTL930X_SMI_10GPHY_POLLING_REGxx_CFG configuration registers. Set them.
Additionally, for RTL 1GBit phys set the RTL930X_SMI_PRVTE_POLLING_CTRL bits
in the poll mask.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
For SFP slots on the RTL9302, the link status is not correctly detected.
Use the link media status instead.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We add the RTL931X sub-target with kernel configuration for
a dual core MIPS InterAptive CPU.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We add HW support routines for the RTL931X SoC family for handling
the Packet Inspection Engine, L2 table handling and STP aging.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We need to store and restore MC memberships in HW when a port joins or
leaves a bridge as well as when it is enabled or disabled, as these
properties should not change in these situations.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
In order to receive STP information at the kernel level, we make sure
that all Bridge Protocol Data Units are copied to the CPU-Port.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Instead of a generic L2 aging configuration function with complex
logic, we implement an individual function for all SoC types.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Add functionality to enable or disable L2 learning offload and port flooding
for RTL83XX.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This adds LAG support for all 4 SoC families, including support
ofr the use of different distribution algorithm for the load-
balancing between individual links.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Use setting functions instead of register numbers in order to clean up the code.
Also use enums to define inner/outer VLAN types and the filter type.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Adds configuration routines for the internal SerDes of the
RTL930X and RTL931X.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Adds a rtl931x_phylink_mac_config for the RTL931X and improve
the handling of the RTL930X phylink configuration. Add separate
handling of the RTL839x since some configurations are different
from the RTL838X.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We were using the PHY-ids (the reg entries in the PHY
sections of the .dts) as the port numbers. Now scan the
ports section in the .dts, and use the actual port numbers,
following the phy-handle to the PHY properties.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
When a port is brought up, read the SDS-id via the phy_device
for a given port and use this to configure the SDS when it
is brought up.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL9300 has a broken R4K MIPS timer interrupt, however, the
R4K clocksource works. We replace the RTL9300 timer with a
Clock Event Timer (CEVT), which is VSMP aware and can be instantiated
as part of brining a VSMTP cpu up instead of the R4K CEVT source.
For this we place the RTL9300 CEVT timer in arch/mips/kernel
together with other MIPS CEVT timers, initialize the SoC IRQs
from a modified smp-mt.c and instantiate each timer as part
of the MIPS time setup in arch/mips/include/asm/time.h instead
of the R4K CEVT, similarly as is done by other MIPS CEVT timers.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Various fixes to enable Ethernet on the RTL931X:
- Network start and stop sequence for RTL931X HW
- MDIO access on RTL931X SoC
- Chip initialization
- SerDes setup
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Do not lock the register structure in IRQ context. It is not
necessary and leads to lockups under SMP load.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Rename the SoC-specific rtl838x_reg structure in the Ethernet
driver to avoid confusion with the structure of the same name
in the DSA driver. New name is: rtl838x_eth_reg
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Setting bits 20 and 23 in a u16 is obviously wrong.
According to https://www.svanheule.net/realtek/cypress/cputag
cpu_tag[2] starts at bit 48 in the cpu-tag structure, so
bit 43 is bit 5 in cpu_tag[2] and bit 40 is bit 8 in
cpu_tag[2].
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Set CONFIG_FORCE_MAX_ZONEORDER setting to 13 to allow larger
contiguous memory allocation for the DMA of the Ethernet
driver. Increase the number of entries in the RX ring
to 300 making use of the larger DMA region now possible for
receiveing packets.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
In order for the Platform includes to be available on
all sub-targets, make them dependent on CONFIG_RTL83XX.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Creates RTL83XX as a basic kernel config parameter for the
RTL838X, RTL839x, RTL930X and RTL931X platforms with respective
configurations for the SoCs, which are introduced in addition.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL9300/RTL9310 I2C controllers have support for 2 independent I2C
masters, each with a fixed SCL pin, that cannot be changed. Each of these
masters can use 8 (RTL9300) or 16 (RTL9310) different pins for SDA.
This multiplexer directly controls the two masters and their shared
IO configuration registers to allow multiplexing between any of these
busses. The two masters cannot be used in parallel as the multiplex
is protected by a standard multiplex lock.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This adds support for the RTL9300 and RTL9310 I2C controller.
The controller implements the SMBus protocol for SMBus transfers
over an I2C bus. The driver supports selecting one of the 2 possible
SCL pins and any of the 8 possible SDA pins. Bus speeds of
100kHz (standard speed) and 400kHz (high speed I2C) are supported.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This patch removes support for the legacy GPIO driver, since now
the gpio-otto driver can be used on all platforms
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
By dropping _machine_restart, users can provide more reliable or
device-specific restart modes.
_machine_halt was already removed in commit f4b687d1f0 ("realtek: use
kernel defined halt"), but quietly reintroduced in commit 8faffa00cb
("realtek: add support for the RTL9300 timer"). Let's remove it again.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Recent versions of Realtek's SDK reset both the ethernet NIC and queues
(SW_NIC_RST and SW_Q_RST bits) when initialising the hardware.
Furthermore, when issuing a CPU reset on the Zyxel GS1900-8 (not
supported by any current driver), the networking part of the SoC is not
reset. This leads to unresponsive network after the restart. By
resetting both the ethernet NIC and queues, networking always comes up
reliably.
Suggested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Commit 03e1d93e07 ("realtek: add driver support for routing
offload") added routing offload for IPv4, but broke IPv6 routing
completely. The routing table is empty and cannot be updated:
root@gs1900-10hp:~# ip -6 route
root@gs1900-10hp:~# ip -6 route add unreachable default
RTNETLINK answers: Invalid argument
As a side effect, this breaks opkg on IPv4 only systems too,
since uclient-fetch fails when there are no IPv6 routes:
root@gs1900-10hp:~# uclient-fetch http://192.168.99.1
Downloading 'http://192.168.99.1'
Failed to send request: Operation not permitted
Fix by returning NOTIFY_DONE when offloading is unsupported, falling
back to default behaviour.
Fixes: 03e1d93e07 ("realtek: add driver support for routing offload")
Signed-off-by: Bjørn Mork <bjorn@mork.no>
The otto GPIO driver does not work with rtl9300 SoCs. Add
the legacy driver again and use that by default in the 9300 .dtsi
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
RTL8393 SoCs older than Revision C hang on accesses to PHYs with PHY address
larger or equal to the CPU-port (52). This will make scanning the MDIO bus
hang forever. Since the RTL8390 platform does not support more than
52 PHYs, return -EIO for phy addresses >= 52. Note that the RTL8390 family
of SoCs has a fixed mapping between port number and PHY-address.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Adds SoC specific routing offload implementations for
RTL8380/90 and RTL9300. RTL83xx supports merely nexthop
routing, RTL9300 full host and prefix routes.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Add generic support for listening to FIB and Event notifier updates and
use this information to hook into the L3 hardware capabilities of the
RTL SoCs.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The ingress filter registers use 2 bits for each port to define the filtering
state, whereas the egress filter uses 1 bit. So for for the ingress filter
the register offset for a given port is:
(port >> 4) << 4: since there are 16 entries in a register of 32 bits
and for the egress filter:
(port >> 5) << 4: since there are 32 entries in a register of 32 bits
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Configure a sane L2 learning configuration upon DSA driver load so that the
switch can start learning L2 addresses. Also configure the correct flood masks
for broadcast and unknown unicast traffice.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This adds RTL93xx-specific MAC configuration routines that allow also configuration
of 10GBit links for phylink. There is support for the Realtek-specific HISGMI
protocol.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This adds support for offloading TC flower by using the Packet Inspection Engine
of the RTL-SoCs. Basic infrastructure support is provide with callbacks to the
tc subsystem and support for HW packet counters.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
All RTL SoCs addresss PHYs via their port number, which is mapped to an
SMI address. Add support for configuring this mapping via the .dts on all
SoCs apart from the 839x, where the mapping to the 64 ports is fixed.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
On RTL83xx enable learning of the MAC source address of the CPU port
from outgoing packets. Add documentation on bit fields. On RTL93xx
enable port-mask usage and the use of internal priority, these
SoCs automatically learn the MAC.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Remove the storm control and attack warnings from the IRQ handler
of the Ethernet driver. There was no consequence to the detection
and the kernel can also handle at least the attacks itself.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This enlarges the size of the TX ring buffer, which prevents warnings
when the buffer runs out of space.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The bootloader can leave the GPIO expander in a state which doesn't have
output drivers enabled so GPIOs will properly work for input but output
operations will have no effect.
To avoid disrupting the boot in case the bootloader left direction and
data registers in an inconsistent state (e.g. pulling SoC's reset to 0)
reconfigure everything as input.
Reviewed-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
dsa_to_port function in 5.10 returns dsa_port from the port list in
dsa_switch_tree, but the tree is built when the switch is registered
by dsa_register_switch and it's null in rtl83xx_mdio_probe.
So, we need to use dsa_to_port after the registration of the switch.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
this patch fixes the following errors when compiling:
- dsa_switch_alloc is removed[1]
- a parameter "enum dsa_tag_protocol mprot" is added to dsa_tag_protocol
in dsa_switch_ops (include/net/dsa.h)
- several paramters are added to "phylink_mac_link_up" in dsa_switch_ops
(include/net/dsa.h)
added:
- int speed
- int duplex
- bool tx_pause
- bool rx_pause
- a parameter "struct switchdev_trans *trans" is added to
port_vlan_filtering in dsa_switch_ops (include/net/dsa.h)
[1]: https://lore.kernel.org/lkml/20191020031941.3805884-17-vivien.didelot@gmail.com/
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
this patch fixes the following errors when compiling:
- "unsigned int txqueue" is added as an additional parameter of
ndo_tx_timeout in net_device_ops (include/linux/netdevice.h)
- "mac_link_state" in phylink_mac_ops (include/linux/phylink.h)
is renamed to "mac_pcs_get_state" and changed the return value
to void from int
- several parameters are added to "mac_link_up" in phylink_mac_ops
(include/linux/phylink.h) and the order of the parameters is
changed
added:
- int speed
- int duplex
- bool tx_pause
- bool rx_pause
- a parameter "phy_interface_t *interface" is added to of_get_phy_mode
(drivers/of/of_net.c) and returns the state instead of phy mode
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The following line is already defined in arch/mips/Kbuild.platforms by
300-mips-add-rtl838x-platform.patch.
platform-$(CONFIG_RTL838X) += rtl838x/
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
A macro with the same name is provided in asm/pgtable.h in Kernel 5.10,
use it and drop from ioremap.h.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
To use backported irq driver, drop old irq driver from realtek target
and call irqchip_init() in setup.c.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
To backport the upstreamed driver (gpio-realtek-otto) from 5.13, drop the
old driver from realtek target.
And, modify 301-gpio-add-rtl838x-driver.patch to remove rtl838x GPIO
support and rename it only for rtl8231 GPIO support.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
To backport the upstreamed driver (spi-realtek-rtl) from 5.12, drop the
old driver from realtek target.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
this patch copies the following files from 5.4 to 5.10:
- config-5.4 -> config-5.10
- files-5.4/ -> files-5.10/
- patches-5.4/ -> patches-5.10/
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[rebase on change in files-5.4]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
