This commit adds support for the OCEDO Koala
SOC: Qualcomm QCA9558 (Scorpion)
RAM: 128MB
FLASH: 16MiB
WLAN1: QCA9558 2.4 GHz 802.11bgn 3x3
WLAN2: QCA9880 5 GHz 802.11nac 3x3
INPUT: RESET button
LED: Power, LAN, WiFi 2.4, WiFi 5, SYS
Serial: Header Next to Black metal shield
Pinout is 3.3V - GND - TX - RX (Arrow Pad is 3.3V)
The Serial setting is 115200-8-N-1.
Tested and working:
- Ethernet
- 2.4 GHz WiFi
- 5 GHz WiFi
- TFTP boot from ramdisk image
- Installation via ramdisk image
- OpenWRT sysupgrade
- Buttons
- LEDs
Installation seems to be possible only through booting an OpenWRT
ramdisk image.
Hold down the reset button while powering on the device. It will load a
ramdisk image named 'koala-uImage-initramfs-lzma.bin' from 192.168.100.8.
Note: depending on the present software, the device might also try to
pull a file called 'koala-uimage-factory'. Only the name differs, it
is still used as a ramdisk image.
Wait for the ramdisk image to boot. OpenWRT can be written to the flash
via sysupgrade or mtd.
Due to the flip-flop bootloader which we not (yet) support, you need to
set the partition the bootloader is selecting. It is possible from the
initramfs image with
> fw_setenv bootcmd run bootcmd_1
Afterwards you can reboot the device.
Signed-off-by: David Bauer <mail@david-bauer.net>
Bit 8/12 of reset controller which is marked as PHY_RESET/SWITCH_RESET
in datasheets will trigger either a reset for builtin switch or assert
an external ETH0_RESET_L/ETH1_RESET_L pin, which are usually connected
to external PHY/switch. None of them should be triggered every time an
interface is brought up in ethernet driver.
Remove PHY reset support from ag71xx and definition for them in dtsi.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Buffalo BHR-4GRV2 is a wired router, based on Qualcomm Atheros
QCA9558.
Ported from ar71xx target.
Specification:
- Qualcomm Atheros QCA9558
- 64 MB of RAM
- 16 MB of Flash
- 5x 10/100/1000 Ethernet
- QCA8337N
- 4x LEDs, 2x keys
- UART header on PCB
- Vcc, TX, RX, GND from LED side
- 115200n8
Flash instruction using factory image:
1. Connect the computer to the LAN port of BHR-4GRV2
2. Connect power cable to BHR-4GRV2 and turn on it
3. Access to "http://192.168.12.1/" and open firmware update
page ("ファームウェア更新")
4. Select the OpenWrt factory image and click update ("更新実行")
button
5. Wait ~120 seconds to complete flashing
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
This adds PLL settings for the ethernet ports of the TP-Link TL-WR1043
v2/v3 and the Openmesh OM5P-AC-v2.
We also change the PLL-settings in the qca9557.dtsi to match the ones
used as default on the ar71xx target.
As of 4b9680f138 those devices have broken ethernet ports as the default
PLL settings defined in the QCA9557.dtsi are applied which are off for
those devices.
Signed-off-by: David Bauer <mail@david-bauer.net>
commit 4b9680f fixed pll settings and the correct pll set
by bootloader is overrided by value in qca9557.dtsi which
is incorrect for Archer C7 and breaks ethernet. Add pll
values for archer c7 to fix ethernet connection.
This individual pll tweak has been cherry picked from github pr 1260
which changes a couple of things in a single commit and should be
ideally split. This commit get archer v7 back and working.
Tested: archer c7 v2
Original combined commit authored by:
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
c7 fix only split out by:
Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
Changed default role of Orange Pi PC2 MSUB port to host (in dts)
Changed default function of Orange Pi PC2 power button to PWR_BTN
Signed-off-by: Antonio Silverio <menion@gmail.com>
CPU: H5 High Performance Quad-core 64-bit Cortex-A53
GPU: Mali450 OpenGL ES 2.0/1.1/1.0, OpenVG 1.1, EGL
Memory: 1GB DDR3 (shared with GPU)
Onboard Storage: TF card (Max. 32GB) / NOR flash(2MB)
Onboard Network: 1000M/100M Ethernet RJ45
USB 2.0 Ports: Three USB 2.0 HOST, one USB 2.0 OTG, HOST mode
role by default in DTS
Buttons: Power Button(SW4) Debug TTL
UART: ..DC-IN..
>[GND][RX][TX] ..HDMI..
Signed-off-by: Antonio Silverio <menion@gmail.com>
When checking the outcome of the PHY autonegotiation status, at803x
currently returns false in case the SGMII side is not established.
Due to a hardware-bug, ag71xx needs to fixup the SoCs SGMII side, which
it can't as it is not aware of the link-establishment.
This commit allows to ignore the SGMII side autonegotiation status to
allow ag71xx to do the fixup work.
Signed-off-by: David Bauer <mail@david-bauer.net>
The QCA955X is affected by a hardware bug which causes link-loss of the
SGMII link between SoC and PHY. This happens on change of link-state or
speed.
It is not really known what causes this bug. It definitely occurs when
using a AR8033 Gigabit Ethernet PHY.
Qualcomm solves this Bug in a similar fashion. We need to apply the fix
on a per-device base via platform-data as performing the fixup work will
break connectivity in case the SGMII interface is connected to a Switch.
This bug was first proposed to be fixed by Sven Eckelmann in 2016.
https://patchwork.ozlabs.org/patch/604782/
Based-on-patch-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Signed-off-by: David Bauer <mail@david-bauer.net>
This commit adds the ability to configure specific functions of the
at803x series ethernet-PHYs, which were previously configured
exclusively with the help of platform-data, via device-tree.
This is needed to fully support existing boards of the ar71xx platform.
Signed-off-by: David Bauer <mail@david-bauer.net>
Backport an upstream fix for a remotely exploitable TCP denial of service
flaw in Linux 4.9+.
The fixes are included in Linux 4.14.59 and later but did not yet end up in
version 4.9.118.
Signed-off-by: Jo-Philipp Wich <jo@mein.io>
The QCA9557 dtsi is currently missing pll-handle and pll-regs for both
eth0 and eth1, therefore PLL settings won't be applied. This commit
fixes this behavior.
Signed-off-by: David Bauer <mail@david-bauer.net>
While finalizing support for the U7623 with 512MB, I made an embarresing
error and configured 1GB RAM for the board. I also forgot to move memory
from the dtsi and to the dts. This commit takes care of my mistakes.
While I am confessing my mistakes, I also note that I made a mistake in
the commit message of the initial U7623 commit. It is the .bin-file, and
not the .gz file that shall be sent to the device via tftp.
v1->v2:
* Remove redundant memory node (thanks Jonas Gorski)
Signed-off-by: Kristian Evensen <kristian.evensen@gmail.com>
Including the tl-wdr3600 image build code just to overwrite most of it
doesn't make much sense and only makes it hard to read.
Furthermore, the tl-wdr4300 image will be marked as compatible with the
tl-wdr3600 this way.
Signed-off-by: Mathias Kresin <dev@kresin.me>
The variables are used in image build recipes and need to be marked as
per devices vars to be stored individual per image define. Otherwise
the last defined variable will be used for all boards.
Signed-off-by: Mathias Kresin <dev@kresin.me>
This patch did the following things:
1. Separate ath9k-leds out of gpio leds so that all other leds will work
before ath9k loded (e.g. during preinit/init stage).
2. Rename wps led to qss since that's how TP-Link mark it.
3. Rename LED prefix to tp-link because that dts is shared by many devices.
4. Rename to wr740n-v1 because v1 is the first and v2 just use the fw of v1.
(This will require a forced sysupgrade if you comes from
the previous wr740n v2 image.)
5. Remove SUPPORTED_DEVICES.
(tl-wr740n-v2 doesn't exist anywhere so it's useless.)
6. Add all WR741ND v1 clones found in ar71xx.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Fix all issues found by the devicetree compiler like wrong address/size
cells as well as wrong/missing/superfluous unit addresses.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Use only the jedec,spi-nor compatible string. Everything else either
never worked or is only support to keep compatibility.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Use the same method for setting queue index pointers consistenly
throughout the source file.
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
This router is called Archer C7 and the tl was used to identify
TP-LINK. Since we have added tplink in dts/board name, the tl
prefix is useless now.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Change lan and it's LED to eth0
It's broken since c7c807cb8c
where I changed the dts but forgot to change default configurations.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
1. Swap eth0/eth1
Both devices are using AR9331, the builtin switch on AR9331 is
connected to gmac1 and gmac1 is named as eth1 in ath79.
PS: gmac1 is eth0 and gmac0 is eth1 in ar71xx because of the
reversed initialization order.
2. Fix the incorrect compatible string in dts
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
phy-handle is used to poll link status. They are useless when
we need fixed-link on these interfaces.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Jonas Gorski commented on the previous patch:
|This is actually the wrong fix and papers over an issue in one of our
|local patches.
|
|We intentionally allow regmap to be built as a module, see
|
|/target/linux/generic/hack-4.14/259-regmap_dynamic.patch
|[...]
|[The regulator code] optionally supports regmap thanks to the stubs
|provided if regmap is disabled - which breaks if you compile regmap
|as a module.
In order to mitigate this issue, this patch reverts the previous patch
and replaces the existing IS_ENABLED(CONFIG_REGMAP) with
IS_REACHABLE(CONFIG_REGMAP). This solves this particular issue as the
regulator code will now automatically fallback to the regmap stubs in
case the kmod-regmap module is enabled, but nothing else sets
CONFIG_REGMAP=y.
Note: There's still a potential issue that this patch doesn't solve:
If someone ever wants to make a OpenWrt kernel package for a
regulator module that requires the REGMAP feature for a target that
doesn't set CONFIG_REGMAP=y but has CONFIG_REGULATOR=y, the resulting
kmod-regulator-xyz package will not work on the target.
Luckily, there aren't any in-tree OpenWrt kernel module packages for
regulators at the moment. On the bright side: regmap is a critical
part nowadays and all new and upcoming architectures require it by
default. This will likely only ever be a problem for legacy targets
and devices that cannot afford to enable REGMAP.
Cc: Jonas Gorski <jonas.gorski@gmail.com>
Cc: John Crispin <john@phrozen.org>
Fixes: d00913d121 ("kernel: modules: fix kmod-regmap")
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
To share mdio addr for IntPHY and ExtPHY,
as described in the documentation (MT7620_ProgrammingGuide.pdf).
(refer: http://download.villagetelco.org/hardware/MT7620/MT7620_ProgrammingGuide.pdf)
when port4 setup to work as gmac mode, dts like:
&gsw {
mediatek,port4 = "gmac";
};
we should set SYSCFG1.GE2_MODE==0x0 (RGMII).
but SYSCFG1.GE2_MODE may have been set to 3(RJ-45) by uboot/default
so we need to re-set it to 0x0
before this changes:
gsw: 4FE + 2GE may not work correctly and MDIO addr 4 cannot be used by ExtPHY
after this changes:
gsw: 4FE + 2GE works and MDIO addr 4 can be used by ExtPHY
Signed-off-by: Chen Minqiang <ptpt52@gmail.com>
When PHY's are defined on the MDIO bus in the DTS, gigabit support was
being masked out for no apparent reason, pegging all such ports to 10/100.
If gigabit support must be disabled for some reason, there should be a
"max-speed" property in the DTS.
Reported-by: James McKenzie <openwrt@madingley.org>
Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
Mediatek has a reference platform that pairs an MT7620A with an MT7530W,
where the latter responds on MDIO address 0x1f while both chips respond on
0x0 to 0x4. The driver special-cases this arrangement to make sure it's
talking to the right chip, but two different ways in two different places.
This patch consolidates the detection without the current requirement of
both tests to be separately satisfied in the DTS.
Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
Starting with kernel 4.4, the use of partitions as direct subnodes of the
mtd device is discouraged and only supported for backward compatiblity
reasons.
Signed-off-by: Alex Maclean <monkeh@monkeh.net>
Fix space vs. tabs issue and trainling whitespaces. Use C style
comments or drop the comments if they explain what is already to see in
the devicetree parameters.
Signed-off-by: Mathias Kresin <dev@kresin.me>
The hardware NAT node has the same reg/unit as the ethernet node. One
of them need to be a child of the other.
Make the hardware NAT node a child of the ethernet node since the it
"reference" the netdev in its properties.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Add the ranges property to the PCI bridges where missing. Add the unit
address to PCI bridge where missing.
Rework the complete rt3883 pci node. Drop the PCI unit nodes from the
dtsi. They are not used by any dts file and should be rather in the dts
than in the SoC dtsi. Express the PCI-PCI bridge in a clean devicetree
syntax. The ralink,pci-slot isn't used by any driver, drop it. Move the
pci interrupt controller out of the pci node. It doesn't share the same
reg and therefore should be an independent/SoC child node.
Move the pci related rt3883 pinctrl setting to the dtsi instead of
defining the very same for each rt3883 board.
If the device_type property is used for PCI units, the unit is treated
as pci bridge which it isn't. Drop it for PCI units.
Reference pci-bridges or the pci node defined in the dtsi instead of
recreating the whole node hierarchy. It allows to change the referenced
node in the dtsi without the need to touch all dts.
Fix the PCI(e) wireless unit addresses. All our PCI(e) wireless chips
are the first device on the bus. The unit address has to be the bus
address instead of the PCI vendor/device id.
Signed-off-by: Mathias Kresin <dev@kresin.me>
