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openwrt/target/linux/bcm63xx/patches-5.4/516-board-bcm6358.patch

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bcm63xx: reorganize board patches into fewer files At the moment, bcm63xx creates one patch for each board to add to board_bcm963xx.c. While this is not really helpful to get an overview in the first place, it is particularly painful if you want to change something for an early file and have to refresh all the later patches accordingly. Since it does not look like these board patches are upstreamed either, this commit consolidates all board additions into one patch per "board". By this, both adding and editing boards should become much simpler, and we drop about 1300 lines of "code" from patches as well. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2020-10-04 16:00:28 +00:00
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
+#include <linux/pci_ids.h>
#include <asm/addrspace.h>
#include <bcm63xx_board.h>
#include <bcm63xx_cpu.h>
@@ -1445,6 +1446,88 @@ static struct board_info __initdata boar
.has_ehci0 = 1,
};
+static struct board_info __initdata board_CPVA642 = {
+ .name = "CPVA642",
+ .expected_cpu_id = 0x6358,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+
+ .has_enet1 = 1,
+ .enet1 = {
+ .has_phy = 1,
+ .phy_id = 0,
+ .force_speed_100 = 1,
+ .force_duplex_full = 1,
+ },
+};
+
+static struct board_info __initdata board_ct6373_1 = {
+ .name = "CT6373-1",
+ .expected_cpu_id = 0x6358,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+
+ .has_enet1 = 1,
+ .enet1 = {
+ .has_phy = 1,
+ .phy_id = 0,
+ .force_speed_100 = 1,
+ .force_duplex_full = 1,
+ },
+
+ .use_fallback_sprom = 1,
+ .fallback_sprom = {
+ .type = SPROM_BCM4318,
+ .pci_bus = 0,
+ .pci_dev = 1,
+ },
+};
+
+/* D-Link DSL-274xB revison C2/C3 */
+static struct board_info __initdata board_dsl_274xb_rev_c = {
+ .name = "AW4139",
+ .expected_cpu_id = 0x6358,
+
+ .has_pci = 1,
+
+ .has_enet1 = 1,
+ .enet1 = {
+ .has_phy = 1,
+ .phy_id = 0,
+ .force_speed_100 = 1,
+ .force_duplex_full = 1,
+ },
+};
+
+/* D-Link DVA-G3810BN/TL */
+static struct board_info __initdata board_DVAG3810BN = {
+ .name = "DVAG3810BN",
+ .expected_cpu_id = 0x6358,
+
+ .has_pccard = 1,
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+
+ .has_enet0 = 1,
+ .enet0 = {
+ .has_phy = 1,
+ .use_internal_phy = 1,
+ },
+
+ .has_enet1 = 1,
+ .enet1 = {
+ .has_phy = 1,
+ .phy_id = 0,
+ .force_speed_100 = 1,
+ .force_duplex_full = 1,
+ },
+};
+
static struct board_info __initdata board_DWVS0 = {
.name = "DWV-S0",
.expected_cpu_id = 0x6358,
@@ -1469,6 +1552,238 @@ static struct board_info __initdata boar
.has_ohci0 = 1,
.has_ehci0 = 1,
};
+
+static struct board_info __initdata board_homehub2a = {
+ .name = "HOMEHUB2A",
+ .expected_cpu_id = 0x6358,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_enet1 = 1,
+ .enet1 = {
+ .has_phy = 1,
+ .phy_id = 0,
+ .force_speed_100 = 1,
+ .force_duplex_full = 1,
+ },
+
+ .use_fallback_sprom = 1,
+ .fallback_sprom = {
+ .type = SPROM_BCM4322,
+ .pci_bus = 0,
+ .pci_dev = 1,
+ },
+};
+
+static struct board_info __initdata board_HW520 = {
+ .name = "HW6358GW_B",
+ .expected_cpu_id = 0x6358,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+
+ .has_enet0 = 1,
+ .enet0 = {
+ .has_phy = 1,
+ .use_internal_phy = 1,
+ },
+
+ .has_enet1 = 1,
+ .enet1 = {
+ .has_phy = 1,
+ .phy_id = 0,
+ .force_speed_100 = 1,
+ .force_duplex_full = 1,
+ },
+
+ .use_fallback_sprom = 1,
+ .fallback_sprom = {
+ .type = SPROM_BCM4318,
+ .pci_bus = 0,
+ .pci_dev = 1,
+ },
+};
+
+static struct board_info __initdata board_HW553 = {
+ .name = "HW553",
+ .expected_cpu_id = 0x6358,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_enet1 = 1,
+ .enet1 = {
+ .has_phy = 1,
+ .phy_id = 0,
+ .force_speed_100 = 1,
+ .force_duplex_full = 1,
+ },
+
+ .use_fallback_sprom = 1,
+ .fallback_sprom = {
+ .type = SPROM_BCM4318,
+ .pci_bus = 0,
+ .pci_dev = 1,
+ },
+};
+
+static struct board_info __initdata board_HW556_A = {
+ .name = "HW556_A",
+ .expected_cpu_id = 0x6358,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_caldata = 1,
+ .caldata = {
+ {
+ .vendor = PCI_VENDOR_ID_ATHEROS,
+ .caldata_offset = 0xf7e000,
+ .slot = 1,
+ .endian_check = 1,
+ .led_pin = 2,
+ .led_active_high = 1,
+ },
+ },
+
+ .has_enet1 = 1,
+ .enet1 = {
+ .has_phy = 1,
+ .phy_id = 0,
+ .force_speed_100 = 1,
+ .force_duplex_full = 1,
+ },
+};
+
+static struct board_info __initdata board_HW556_B = {
+ .name = "HW556_B",
+ .expected_cpu_id = 0x6358,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_caldata = 1,
+ .caldata = {
+ {
+ .vendor = PCI_VENDOR_ID_ATHEROS,
+ .caldata_offset = 0xefe000,
+ .slot = 1,
+ .endian_check = 1,
+ .led_pin = 2,
+ .led_active_high = 1,
+ },
+ },
+
+ .has_enet1 = 1,
+ .enet1 = {
+ .has_phy = 1,
+ .phy_id = 0,
+ .force_speed_100 = 1,
+ .force_duplex_full = 1,
+ },
+};
+
+static struct board_info __initdata board_HW556_C = {
+ .name = "HW556_C",
+ .expected_cpu_id = 0x6358,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_caldata = 1,
+ .caldata = {
+ {
+ .vendor = PCI_VENDOR_ID_RALINK,
+ .caldata_offset = 0xeffe00,
+ .slot = 1,
+ .eeprom = "rt2x00.eeprom",
+ },
+ },
+
+ .has_enet1 = 1,
+ .enet1 = {
+ .has_phy = 1,
+ .phy_id = 0,
+ .force_speed_100 = 1,
+ .force_duplex_full = 1,
+ },
+};
+
+static struct board_info __initdata board_nb4_ser_r0 = {
+ .name = "NB4-SER-r0",
+ .expected_cpu_id = 0x6358,
+
+ .has_pccard = 1,
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_enet0 = 1,
+ .enet0 = {
+ .has_phy = 1,
+ .use_internal_phy = 1,
+ },
+
+ .has_enet1 = 1,
+ .enet1 = {
+ .has_phy = 1,
+ .phy_id = 0,
+ .force_speed_100 = 1,
+ .force_duplex_full = 1,
+ },
+};
+
+static struct board_info __initdata board_nb4_fxc_r1 = {
+ .name = "NB4-FXC-r1",
+ .expected_cpu_id = 0x6358,
+
+ .has_pccard = 1,
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_enet0 = 1,
+ .enet0 = {
+ .has_phy = 1,
+ .use_internal_phy = 1,
+ },
+
+ .has_enet1 = 1,
+ .enet1 = {
+ .has_phy = 1,
+ .phy_id = 0,
+ .force_speed_100 = 1,
+ .force_duplex_full = 1,
+ },
+};
+
+ /* T-Home Speedport W 303V Typ B */
+static struct board_info __initdata board_spw303v = {
+ .name = "96358-502V",
+ .expected_cpu_id = 0x6358,
+
+ .has_pci = 1,
+
+ .has_enet0 = 1,
+ .enet0 = {
+ .has_phy = 1,
+ .use_internal_phy = 1,
+ },
+};
#endif /* CONFIG_BCM63XX_CPU_6358 */
/*
@@ -1535,7 +1850,20 @@ static const struct board_info __initcon
&board_96358vw,
&board_96358vw2,
&board_AGPFS0,
+ &board_CPVA642,
+ &board_ct6373_1,
+ &board_dsl_274xb_rev_c,
+ &board_DVAG3810BN,
&board_DWVS0,
+ &board_homehub2a,
+ &board_HW520,
+ &board_HW553,
+ &board_HW556_A,
+ &board_HW556_B,
+ &board_HW556_C,
+ &board_nb4_ser_r0,
+ &board_nb4_fxc_r1,
+ &board_spw303v,
#endif /* CONFIG_BCM63XX_CPU_6358 */
};
bcm63xx: Add support for D-Link DSL-2750u rev C1 This adds support for the D-Link DSL-2750u rev C1. (https://deviwiki.com/wiki/D-Link_DSL-2750U_rev_C1) It uses the same hardware as ADB P.DG A4001N. CPU: Broadcom BCM63281 (320 MHz) RAM: 32M (Winbond W9725G6JB) Flash: 8M (MXIC MX25L6445E) Ethernet: 4x 100 Mbps Wireless: 802.11b/g/n: BCM43225 USB: 1x 2.0 Flash instructions: 1. Assign static IP 192.168.1.100 to PC 2. Unplug the power source 3. Press the RESET button at the router, don't release it yet! 4. Plug the power source.Wait some seconds 5. Release the RESET button 6. Browse to http://192.168.1.1 7. Send the openwrt-bcm63xx-generic-DSL2750U-C1-squashfs-cfe.bin and wait some minutes until the firmware upgrade finish. Signed-off-by: Ahmed Naseef <naseefkm@gmail.com> [DTS improvements, proper board patch, refresh patches] Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2020-08-18 12:22:20 +00:00
@@ -1608,11 +1936,24 @@ static struct of_device_id const bcm963x
bcm63xx: reorganize board patches into fewer files At the moment, bcm63xx creates one patch for each board to add to board_bcm963xx.c. While this is not really helpful to get an overview in the first place, it is particularly painful if you want to change something for an early file and have to refresh all the later patches accordingly. Since it does not look like these board patches are upstreamed either, this commit consolidates all board additions into one patch per "board". By this, both adding and editing boards should become much simpler, and we drop about 1300 lines of "code" from patches as well. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2020-10-04 16:00:28 +00:00
{ .compatible = "alcatel,rg100a", .data = &board_96358vw2, },
{ .compatible = "brcm,bcm96358vw", .data = &board_96358vw, },
{ .compatible = "brcm,bcm96358vw2", .data = &board_96358vw2, },
+ { .compatible = "bt,home-hub-2-a", .data = &board_homehub2a, },
+ { .compatible = "comtrend,ct-6373", .data = &board_ct6373_1, },
{ .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, },
+ { .compatible = "d-link,dsl-274xb-c2", .data = &board_dsl_274xb_rev_c, },
+ { .compatible = "d-link,dva-g3810bn-tl", .data = &board_DVAG3810BN, },
+ { .compatible = "huawei,echolife-hg520v", .data = &board_HW520, },
+ { .compatible = "huawei,echolife-hg553", .data = &board_HW553, },
+ { .compatible = "huawei,echolife-hg556a-a", .data = &board_HW556_A, },
+ { .compatible = "huawei,echolife-hg556a-b", .data = &board_HW556_B, },
+ { .compatible = "huawei,echolife-hg556a-c", .data = &board_HW556_C, },
{ .compatible = "pirelli,a226g", .data = &board_DWVS0, },
{ .compatible = "pirelli,a226m", .data = &board_DWVS0, },
{ .compatible = "pirelli,a226m-fwb", .data = &board_DWVS0, },
{ .compatible = "pirelli,agpf-s0", .data = &board_AGPFS0, },
+ { .compatible = "sfr,neufbox-4-sercomm-r0", .data = &board_nb4_ser_r0, },
+ { .compatible = "sfr,neufbox-4-foxconn-r1", .data = &board_nb4_fxc_r1, },
+ { .compatible = "t-com,speedport-w-303v", .data = &board_spw303v, },
+ { .compatible = "telsey,cpva642", .data = &board_CPVA642, },
#endif /* CONFIG_BCM63XX_CPU_6358 */
#ifdef CONFIG_BCM63XX_CPU_6362
#endif /* CONFIG_BCM63XX_CPU_6362 */
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