Xianjun Jiao 7b2f8bdfff Align the inital actual_tx_lo/actual_rx_lo to rf_init_11n.sh: ...

Make it far from our usual 2.4/5GHz to force ad9361 to calibration while up in 2.4/5GHz due to large tuning offset from the original frequency (1GHz)

2022-03-28 15:20:03 +02:00

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ad9361

Add modified ad9361_conv.c of our own:

2022-03-26 20:34:55 +01:00

openofdm_rx

turn on soft decoding by default in openofdm_rx.c driver

2021-04-05 21:41:31 +02:00

openofdm_tx

Update openofdm_tx.c

2021-02-03 15:38:47 +01:00

rx_intf

Fix various typos

2021-02-04 20:41:51 +01:00

side_ch

Scripts are adapted for SW HW decouple

2021-10-20 22:50:30 +02:00

tx_intf

use FPGA fifo count registers instead of software queue_cnt

2022-01-06 15:07:50 +01:00

xilinx_dma

Scripts are adapted for SW HW decouple

2021-10-20 22:50:30 +02:00

xpu

A-MPDU rx aggregation support

2022-01-06 14:13:24 +01:00

hw_def.h

use FPGA fifo count registers instead of software queue_cnt

2022-01-06 15:07:50 +01:00

make_all.sh

Avoid the git_rev.h issue:

2022-03-26 20:47:02 +01:00

Makefile

prepare upgrade

2020-04-27 09:37:04 +02:00

sdr.c

Align the inital actual_tx_lo/actual_rx_lo to rf_init_11n.sh:

2022-03-28 15:20:03 +02:00

sdr.h

Add the missing rf_reg_val in priv

2022-03-28 14:57:49 +02:00

sdrctl_intf.c

Move sdrctl testmode cmd out to sdrctl_intf.c

2022-03-28 12:46:18 +02:00

sysfs_intf.c

Add sysfs file based driver/FPGA access interface

2022-03-28 12:46:49 +02:00