Xianjun Jiao 2ae501ca2e Disable TID in sdr.c:
By default the TID is disabled in FPGA, because we currently try to TX and RX traffic for all TIDs. So, the TID related operations in sdr.c are removed.
2022-03-28 14:02:23 +02:00
..
2021-02-03 15:38:47 +01:00
2021-02-04 20:41:51 +01:00
2022-01-06 14:13:24 +01:00
2022-03-26 20:47:02 +01:00
2020-04-27 09:37:04 +02:00
2022-03-28 14:02:23 +02:00
2022-03-28 14:02:23 +02:00