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• 85d28e4373 Add freq offset (phase_offset FPGA) to: rx pkt dmesg nlnet_sw_2025 Xianjun Jiao 2025-04-15 18:10:46 +02:00
• 4b79376d86 Add sudo to wgd.sh in case some linux needs it Xianjun Jiao 2025-04-16 19:55:07 +01:00
• fd1b030205 Reserve some logic for future hardware: in prepare_kernel.sh Xianjun Jiao 2025-04-16 14:17:47 +01:00
• b4e4e6761c Change 1 to true to avoid bash error Xianjun Jiao 2025-04-15 18:52:53 +01:00
• 08b49e16cc Add Xilinx ENV as define, and > Move to 2022_R2 for prepare_kernel.sh Xianjun Jiao 2025-04-11 13:46:42 +01:00
• 7007a52f63 Reserve some logic for future hardware: in load_fpga_img.sh Xianjun Jiao 2025-04-10 11:07:07 +01:00
• 0ae4b61af7 Add Xilinx ENV as define, and > Move to 2022_R2 for drv_and_fpga_package_gen.sh Xianjun Jiao 2025-04-09 19:22:01 +01:00
• 02752dc8f7 Make our script capable of using any .xsa file name: originally it assumes system_top.xsa Xianjun Jiao 2025-04-09 18:40:36 +01:00
• 5ec54bc0ef Add Xilinx ENV as define, and > Move to 2022_R2 for make_all.sh Xianjun Jiao 2025-04-09 18:26:28 +01:00
• 99c08d7ae4 Add Xilinx ENV as define, and Move to 2022_R2 Xianjun Jiao 2025-04-09 12:17:23 +01:00
• ea32274930 Fix a bug under injection where control->sta is NULL Xianjun Jiao 2025-04-09 11:32:20 +01:00
• 7b1333150c Add hardware_type into driver: Reserve for future hardwares Xianjun Jiao 2025-04-08 16:07:36 +01:00
• c6111ec7cb reformat sdr.c Xianjun Jiao 2025-04-07 19:02:33 +01:00
• 71c3bec811 reformat sdrctl_intf.c Xianjun Jiao 2025-04-07 16:27:28 +01:00
• 56ebdf7153 reformat sdr.h Xianjun Jiao 2025-04-04 13:30:32 +01:00
• 424db77a39 reformat hw_def.h Xianjun Jiao 2025-04-03 17:06:13 +01:00
• 5efc9abbbd reformat tx_intf.c Xianjun Jiao 2025-04-03 10:55:17 +01:00
• ffdb1c2585 Add more outputs to: Matlab script test_side_info_file_display.m Xianjun Jiao 2025-04-03 10:44:40 +01:00
• a3701aa383 +x mode for agc_settings.sh Xianjun Jiao 2025-04-02 16:10:53 +01:00
• 7ee268f505 Get new build_zynqmp_boot_bin.sh from: https://wiki.analog.com/resources/tools-software/linux-software/build-the-zynqmp-boot-image Xianjun Jiao 2025-04-02 15:55:18 +01:00
• be371b37c4 Let rf reg also set restrict freq Xianjun Jiao 2025-04-02 14:22:31 +01:00
• 658c4e1200 Avoid hw_init of all modules causing nonconsistency Xianjun Jiao 2025-04-02 11:34:47 +01:00
• d98d287dcc Resolve the issue xpu channel reg4 value 44: Remove this XPU_REG_BAND_CHANNEL_write in xpu.c, because 1. the 44 for channel field is out dated. Now the channel actually should be frequency in MHz 2. PROBLEM! this hw_init call in openwifi_start will cause lossing consistency between XPU register and (priv->use_short_slot<<24)|(priv->band<<16)|(priv->actual_rx_lo) Xianjun Jiao 2025-04-02 11:22:20 +01:00
• 25b678e27f Make band change consistent to actual_rx_lo: and actual_tx_lo. also remove unused priv->channel Xianjun Jiao 2025-04-02 11:03:21 +01:00
• e2bf29f067 Make 2.4 5GHz decision point middle: to Avoid the freq close to the low edge of 5GHz being treated as 2.4GHz Xianjun Jiao 2025-04-01 11:41:13 +01:00
• eaec960312 Improve iq_capture_2ant.py Xianjun Jiao 2025-03-31 19:37:50 +01:00
• 5d456058d5 Add filename display in: test_iq_2ant_file_display.m Xianjun Jiao 2025-03-31 17:02:59 +01:00
• 00b8b7e61a chan_to_pl is not used in side_ch Xianjun Jiao 2025-03-31 10:10:08 +01:00
• 1b4ea93842 Support full addr1/2 for inject_80211.c Xianjun Jiao 2025-03-28 18:47:43 +01:00
• 1164b93509 Let mat file follow input for: test_iq_file_display.m Xianjun Jiao 2025-03-28 17:46:44 +01:00
• c608966cde Correct the LUT_SIZE in: iq_capture_freq_offset.py. And add comments on chosing correct LUT_SIZE Xianjun Jiao 2025-03-28 10:07:04 +01:00
• 8b165cff9c Avoid non-consistent freq override Xianjun Jiao 2025-03-27 16:55:52 +01:00
• 42c640feff Adapt ACK tx timing in xpu.c Xianjun Jiao 2025-03-27 16:36:07 +01:00
• 13fe0cf74a Improve plot in test_iq_file_display.m Xianjun Jiao 2025-03-27 14:03:37 +01:00
• 498d5bbb61 Improve plot in iq_capture.py Xianjun Jiao 2025-03-26 18:04:50 +01:00
• af2597b829 Add fcs ok happen plot in test_iq_file_display.m Xianjun Jiao 2025-03-26 15:00:04 +01:00
• 51fe91b65e fix the directory in scripts Xianjun Jiao 2025-03-26 12:18:43 +01:00
• 7e619d3169 Fix the wrong directory in agc_settings.sh xjiao 2025-03-26 10:26:51 +01:00
• 1a7a7c3dc8 replace tx_bb by fcs_ok according to fpga change Xianjun Jiao 2025-03-25 19:43:49 +01:00
• f96061ed24 Adding support for IPv6 in kernel config file Jetmir Haxhibeqiri 2025-03-24 16:35:20 +01:00
• 0499dbf2f4 Put verified adi-linux commit for tsn prepare_kernel.sh Xianjun Jiao 2025-03-24 14:51:12 +01:00
• c850310829 Update 64bit kernel config to solve: RSSI/rate issue: https://github.ugent.be/xjiao/openwifi/issues/166 Xianjun Jiao 2025-03-24 12:21:43 +01:00
• 8380d2bd3a Update data kernel config to solve: RSSI/rate issue: https://github.ugent.be/xjiao/openwifi/issues/166 Xianjun Jiao 2025-03-21 17:19:09 +01:00
• 97bb6a4e4d Fix the directory for calling agc_settings.sh Xianjun Jiao 2025-03-21 14:59:44 +01:00
• b5d8ef2809 Improve agc for PER at certain RSSI: Change the agc preamble from 32 to 16. The reason: With agc preamble 32, AWGN channel MCS7 will have high PER (~50%) at RSSI range -52~-54dBm. it is not a soly issue of AGC, but also related to the FO estimation. Because forced FO value could reduce the PER to zero. Our future LTF based FO estimation is expected to solve this issue. Changing the agc preamble from 32 to 16 also help a lot on this: PER <=~10%. Xianjun Jiao 2025-03-20 17:57:21 +01:00
• 2ae7b71c83 Add hack/reset at the end of agc_settings.sh Xianjun Jiao 2025-03-20 17:42:03 +01:00
• e2ac268e9d add agc setting to other on boar scripts Xianjun Jiao 2025-03-20 14:24:28 +01:00
• 3f597ce02d Lower the default sensitivity th from -85 to -95: due to performance is much better (can work around -90dBm) Xianjun Jiao 2025-03-19 19:32:40 +01:00
• 61e5bbe8ce Add new agc settings at the end of wgd.sh Xianjun Jiao 2025-03-19 17:48:49 +01:00
• 997de19508 Improved agc settings for sensitivity in signaling mode: - The sensitivity is as good as fixed optimal gain and non signaling. - register 0x15c: 0x70 --> 0x71. Increase the preamble length from 16 to 32 for better power measurement accuracy. - register 0x101: 0x8A --> 0x0C. Digital saturation does not cause a gain decrease; Add -2dB to the AGC Lock Level to avoid clipping high PAPR OFDM signal. - register 0x114: 0x30 --> 0xB0. Don’t unlock gain if ADC Ovrg in State 5. - DO NOT do this! register 0x110: 0x48 --> 0x4A. Don’t Unlock Gain if Lg ADC or LMT Ovrg in State 5. (Otherwise: did not acknowledge authentication response) Xianjun Jiao 2025-03-19 16:07:25 +01:00
• 6d582e8e4d Force ht smoothing for receiver to have better sensitivity Xianjun Jiao 2025-03-19 15:35:21 +01:00
• 5d44de5165 Use new gui lib to avoid freezing plot. xjiao 2025-03-19 10:55:13 +01:00
• 92a8ac736f Add LUT_SIZE to easily switch different lut size Xianjun Jiao 2025-03-18 14:31:55 +01:00
• 034a6f99d7 Python: use TkAgg as GUI backend Fixes unresponsiveness thavinga 2025-03-18 13:59:04 +01:00
• 01f18ce1bd Add show_iq_snr.m to show SNR after: test_iq_file_display.m Xianjun Jiao 2025-03-17 17:04:04 +01:00
• 859841ce5e ZynqMP: Configure Xilinx DMA in kernel as module instead of built-in thavinga 2025-03-14 14:11:41 +01:00
• f65d4ae5b5 Add PER calculation in rx_stat_show.sh Xianjun Jiao 2025-03-13 18:09:29 +01:00
• 75b4cf00fb Update set_rx_gain_auto.sh by hacking ad9361 according: https://github.ugent.be/xjiao/openwifi/issues/148 Xianjun Jiao 2025-03-13 13:38:33 +01:00
• d4579aa869 Update iq capture scripts according to new hw Xianjun Jiao 2025-03-13 12:16:58 +01:00
• 1deaeb376c New dac intf is faster, tx ack waiting time increased Xianjun Jiao 2025-03-13 10:25:14 +01:00
• ccd894d826 Add comments into iq_capture_freq_offset.py: while using totally clean channel (like chamber or non-standard frequency), long preamble detection could also be a good trigger condition. Xianjun Jiao 2025-03-12 17:31:31 +01:00
• d4c0fbb52b Always let rx interrupt reports legal freq/band: It is important for openwifi to connect cmw270 via non-standard frequency Xianjun Jiao 2025-03-11 19:57:40 +01:00
• c39cfd6a83 Add sync short phase offset th in driver for watch dog Xianjun Jiao 2025-03-10 11:40:39 +01:00
• 37a2576c44 Make ltf FO estimation based on long preamble detected flag: demod_is_ongoing Xianjun Jiao 2025-03-07 17:28:58 +01:00
• 0c00ce9575 Add phase_offset check and override scripts Xianjun Jiao 2025-03-07 13:45:51 +01:00
• aa21e8cb40 Add script to switch between default and optimized AGC settings thavinga 2025-03-07 12:15:36 +01:00
• 0343eb15b6 Avoid loading ad9361_drv.ko because it is part of new kernel Xianjun Jiao 2025-03-05 17:32:13 +01:00
• afc84cc0f1 The optimal fft_win_shift is now 4 after: all optimizations, like rotation after fft, etc. Xianjun Jiao 2025-03-05 14:27:06 +01:00
• a5e0991b22 Also save .mat while check ACK timing Xianjun Jiao 2025-03-05 13:00:25 +01:00
• c491759016 Re-calibrate the ACK timing after merging LLR Xianjun Jiao 2025-03-04 18:02:50 +01:00
• 478ee06a4e Add scripts and update README to ease: transfer kernel/devicetree/fpga/driver on board Xianjun Jiao 2025-03-04 16:38:26 +01:00
• fc0eb1fd2a Necessary changes for ADI Linux kernel 2022_R2 Xianjun Jiao 2025-03-04 15:25:18 +01:00
• 70cb2fa99f Update device trees for optimized AGC settings thavinga 2025-03-03 18:00:37 +01:00
• e4ed4a34a8 Update ADI kernel patches for missing AGC setting thavinga 2025-02-28 16:02:48 +01:00
• 3f266966d6 Add note about enabling statistics before rx_gain_show.sh thavinga 2025-02-27 12:06:08 +01:00
• ef5722e6ac Add driver info to git info thavinga 2025-02-27 11:57:56 +01:00
• 08c886eae1 Add option to give file postfix for drv_and_fpga_package_gen.sh thavinga 2025-02-26 16:53:47 +01:00
• 30b492d3aa Make ack timing work with tx_control_state 5: RECV_ACK_WAIT_SIG_VALID Xianjun Jiao 2025-02-26 15:30:16 +01:00
• 30db65945b Unwrap each CSI vector in the matrix separately thavinga 2025-02-26 10:25:54 +01:00
• c7ce4b2bfc Side info display: unwrap phase, set DC to 0 thavinga 2025-02-26 10:00:13 +01:00
• d16217b7aa Swap positon of phy_hdr_config and tx_config: to align better with 80211ax driver Xianjun Jiao 2025-02-25 14:36:01 +01:00
• fb4cc3e54d improve (force)use_cts_protect code efficiency Xianjun Jiao 2025-02-24 16:32:21 +01:00
• 380eec74e8 improve the LARGE/SMALL_FPGA detection in driver Xianjun Jiao 2025-02-24 13:29:31 +01:00
• 77769f9dcb change some u16 to u8 Xianjun Jiao 2025-02-24 10:03:37 +01:00
• bb3e53ba4d add short gi config into driver test_mode argument Xianjun Jiao 2025-02-20 18:49:04 +01:00
• 3b510cfa8a Update side_ch scripts for this discussion: https://github.com/open-sdr/openwifi/discussions/344 Xianjun Jiao 2025-02-19 18:30:12 +01:00
• 8f959713dc Improve the ACK gap calculation parameter Xianjun Jiao 2025-02-19 15:38:43 +01:00
• a424d7bb3b Add timestamp as return argument of .m Xianjun Jiao 2025-02-19 15:17:43 +01:00
• b01c227660 Change the ACK tx timing in xpu driver: according to the ACK timing analysis results of HT Xianjun Jiao 2025-02-19 12:40:13 +01:00
• cfc73a3359 Add Matlab script for ACK timing analysis Xianjun Jiao 2025-02-18 15:16:16 +01:00
• bd3f48f407 Change the default data type to uint16 Xianjun Jiao 2025-02-18 13:24:23 +01:00
• 4cfdc1c47c Update prepare_kernel to ignore warning in mac80211 thavinga 2025-02-17 14:43:42 +01:00
• b102ce3460 write Fc to lower 16 bit of XPU_REG_BAND_CHANNEL register Wei Liu 2025-02-14 19:45:38 +01:00
• 2433d43ded
  Add CSI fuzzer counter attack paper. master Jiao Xianjun 2025-03-21 20:47:50 +01:00
• 653e3eed2b
  Add TWT survey paper Jiao Xianjun 2025-03-19 08:37:31 +01:00
• b3bfd95b39
  Jesus A. Armenta-Garcia sensing survey paper Jiao Xianjun 2025-03-12 11:08:51 +01:00
• 19e2e96f87
  Add Tianyu testbed survey paper Jiao Xianjun 2025-03-12 11:05:38 +01:00
• e46ef8cb3c
  Add Hao Zhou LLM for telecomm paper. Jiao Xianjun 2025-03-12 09:42:40 +01:00
• 8aadf2e653
  Add Renato secure Wi-Fi sensing paper Jiao Xianjun 2025-03-12 09:39:58 +01:00
• 70c0f75117
  Add Yongchao openwifi RIC TSN paper Jiao Xianjun 2025-03-12 09:32:31 +01:00