ExternalVendorCode/openwifi
1
0
Fork 0
mirror of https://github.com/open-sdr/openwifi.git synced 2025-04-19 08:06:15 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Add sync short phase offset th in driver for watch dog

Browse Source
This commit is contained in:
Xianjun Jiao 2025-03-10 11:40:39 +01:00
parent 37a2576c44
commit c39cfd6a83
2 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
driver/hw_def.h
View File

@ -206,6 +206,7 @@ const char *openofdm_rx_compatible_str = "sdr,openofdm_rx";
#define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR (3*4)
#define OPENOFDM_RX_REG_SOFT_DECODING_ADDR (4*4)
#define OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR (5*4)
#define OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_ADDR (18*4)
#define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4)
enum openofdm_rx_mode {
@ -242,6 +243,7 @@ enum openofdm_rx_mode {
#define OPENOFDM_RX_MIN_PLATEAU_INIT 100
#define OPENOFDM_RX_FFT_WIN_SHIFT_INIT 4
#define OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH 48
#define OPENOFDM_RX_PHASE_OFFSET_ABS_TH 11
#define OPENWIFI_MAX_SIGNAL_LEN_TH 1700 //Packet longer than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf
@ -262,6 +264,7 @@ struct openofdm_rx_driver_api {
void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value);
void (*OPENOFDM_RX_REG_SOFT_DECODING_write)(u32 value);
void (*OPENOFDM_RX_REG_FFT_WIN_SHIFT_write)(u32 value);
void (*OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write)(u32 value);
};
// ---------------------------------------openofdm tx-------------------------------

5
driver/openofdm_rx/openofdm_rx.c
View File

@ -58,6 +58,9 @@ static inline void OPENOFDM_RX_REG_SOFT_DECODING_write(u32 Data) {
static inline void OPENOFDM_RX_REG_FFT_WIN_SHIFT_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR, Data);
}
static inline void OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_ADDR, Data);
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,openofdm_rx", },
{}
@ -98,6 +101,7 @@ static inline u32 hw_init(enum openofdm_rx_mode mode){
openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT);
openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|(OPENWIFI_MIN_SIGNAL_LEN_TH<<12)|1); //bit1 enable soft decoding; bit15~12 min pkt length threshold; bit31~16 max pkt length threshold
openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write((OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH<<4)|OPENOFDM_RX_FFT_WIN_SHIFT_INIT);
openofdm_rx_api->OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write(OPENOFDM_RX_PHASE_OFFSET_ABS_TH);
//rst
for (i=0;i<8;i++)
@ -144,6 +148,7 @@ static int dev_probe(struct platform_device *pdev)
openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write;
openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write=OPENOFDM_RX_REG_SOFT_DECODING_write;
openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write=OPENOFDM_RX_REG_FFT_WIN_SHIFT_write;
openofdm_rx_api->OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write=OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);