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Avoid hw_init of all modules causing nonconsistency

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This commit is contained in:
Xianjun Jiao 2025-04-02 11:34:47 +01:00
parent d98d287dcc
commit 658c4e1200
4 changed files with 22 additions and 10 deletions
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7
driver/openofdm_rx/openofdm_rx.c
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@ -98,8 +98,11 @@ static inline u32 hw_init(enum openofdm_rx_mode mode){
// 1) power threshold configuration and reset
openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write(1); //bit1 of slv_reg1: force ht smoothing to have better sensitivity
openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|OPENOFDM_RX_POWER_THRES_INIT); // turn on signal watchdog by default
openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT);
// Remove OPENOFDM_RX_REG_POWER_THRES_write to avoid hw_init call in openwifi_start causing inconsistency
// openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|OPENOFDM_RX_POWER_THRES_INIT); // turn on signal watchdog by default
openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT);
openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|(OPENWIFI_MIN_SIGNAL_LEN_TH<<12)|1); //bit1 enable soft decoding; bit15~12 min pkt length threshold; bit31~16 max pkt length threshold
openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write((OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH<<4)|OPENOFDM_RX_FFT_WIN_SHIFT_INIT);
openofdm_rx_api->OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write(OPENOFDM_RX_PHASE_OFFSET_ABS_TH);

4
driver/rx_intf/rx_intf.c
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@ -324,7 +324,9 @@ static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);
rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(1<<8);
rx_intf_api->RX_INTF_REG_BB_GAIN_write(4);
rx_intf_api->RX_INTF_REG_ANT_SEL_write(ant_sel);
// Remove RX_INTF_REG_ANT_SEL_write to avoid hw_init call in openwifi_start causing inconsistency
// rx_intf_api->RX_INTF_REG_ANT_SEL_write(ant_sel);
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0x14);//rst m/s axis
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0);

8
driver/tx_intf/tx_intf.c
View File

@ -313,7 +313,9 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_sym
tx_intf_api->TX_INTF_REG_CSI_FUZZER_write(0);
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(16*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed
tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config);
// Remove TX_INTF_REG_TX_CONFIG_write to avoid hw_init call in openwifi_start causing inconsistency
// tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config);
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);
tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0);
tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write(420);
@ -344,7 +346,9 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_sym
// So, a conservative bb_gain 250 should be used
tx_intf_api->TX_INTF_REG_BB_GAIN_write(250);
tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel);
// Remove TX_INTF_REG_ANT_SEL_write to avoid hw_init call in openwifi_start causing inconsistency
// tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel);
tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write((1<<3)|(2<<4));
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0x434);
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);

13
driver/xpu/xpu.c
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@ -276,7 +276,7 @@ EXPORT_SYMBOL(xpu_api);
static inline u32 hw_init(enum xpu_mode mode){
int err=0, i, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay;
u32 filter_flag = 0;
// u32 filter_flag = 0;
printk("%s hw_init mode %d\n", xpu_compatible_str, mode);
@ -321,8 +321,11 @@ static inline u32 hw_init(enum xpu_mode mode){
MY_BEACON = 14b01000000000000,
MONITOR_ALL = 14b10000000000000;
#endif
filter_flag = (FIF_ALLMULTI|FIF_FCSFAIL|FIF_PLCPFAIL|FIF_BCN_PRBRESP_PROMISC|FIF_CONTROL|FIF_OTHER_BSS|FIF_PSPOLL|FIF_PROBE_REQ|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MY_BEACON|MONITOR_ALL);
xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag);
// Remove XPU_REG_FILTER_FLAG_write to avoid hw_init call in openwifi_start causing inconsistency
// filter_flag = (FIF_ALLMULTI|FIF_FCSFAIL|FIF_PLCPFAIL|FIF_BCN_PRBRESP_PROMISC|FIF_CONTROL|FIF_OTHER_BSS|FIF_PSPOLL|FIF_PROBE_REQ|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MY_BEACON|MONITOR_ALL);
// xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag);
xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write(0xB<<16);//6M 1011:0xB
// after send data frame wait for ACK, this will be set in real time in function ad9361_rf_set_channel
@ -359,9 +362,9 @@ static inline u32 hw_init(enum xpu_mode mode){
printk("%s hw_init mode %d is wrong!\n", xpu_compatible_str, mode);
err=1;
}
// Remove this XPU_REG_BAND_CHANNEL_write, because
// Remove this XPU_REG_BAND_CHANNEL_write in xpu.c, because
// 1. the 44 for channel field is out dated. Now the channel actually should be frequency in MHz
// 2. PROBLEM! this call in openwifi_start will cause lossing consistency between XPU register and
// 2. PROBLEM! this hw_init call in openwifi_start will cause lossing consistency between XPU register and
// (priv->use_short_slot<<24)|(priv->band<<16)|(priv->actual_rx_lo)
// xpu_api->XPU_REG_BAND_CHANNEL_write((false<<24)|(BAND_5_8GHZ<<16)|44);//use_short_slot==false; 5.8GHz; channel 44 -- default setting to sync with priv->band/channel/use_short_slot