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Author	SHA1	Message	Date
mmehari	e17fdc17d5	Connecting a client to openwifi AP in 2.4GHz	2020-01-09 14:07:15 +01:00
Xianjun Jiao	736cca8262	track the correct FPGA/openwifi-hw revision	2020-01-07 14:21:34 +01:00
Xianjun Jiao	2a1e074623	fix the potential memory access over boundary issue of openwifi_rx_interrupt and make necessary configuration for new FPGA that tx sending out I/Q immediately after tx_start which achieves 10us SIFS in 2.4GHz	2020-01-07 14:17:08 +01:00
Jiao Xianjun	a984b3fbc7	Update README.md	2020-01-07 12:04:26 +01:00
Jiao Xianjun	149fafc0a7	add tested mode: Monitor	2020-01-07 10:31:52 +01:00
Jiao Xianjun	02d858a71a	Update README.md	2020-01-06 20:52:13 +01:00
Jiao Xianjun	9d96e69257	add more reminder of channel list change	2020-01-05 14:24:04 +01:00
Jiao Xianjun	0273d86243	change monitor mode description and add regulation and frequency config	2020-01-05 14:20:36 +01:00
Jiao Xianjun	baca0e72e9	Update README.md	2020-01-05 13:02:28 +01:00
Xianjun Jiao	31ae0e6cd6	add better explanation in README about why a symbol link might be needed for directory /lib/modules/4.14.0-g4220d5d24c6c	2020-01-03 21:18:13 +01:00
Xianjun Jiao	2054f92c88	Fix the bug for monitor mode in driver sdr.c openwifi_configure_filter() function. Seems like monitor mode will create and use a new virtual interface, so priv-vif[0] is not valid anymore when monitor mode start and call openwifi_configure_filter()	2020-01-03 18:53:21 +01:00
Jiao Xianjun	365a7066be	Update README.md	2020-01-03 15:58:59 +01:00
Jiao Xianjun	44dff4bd48	add cite format	2019-12-25 09:32:53 +01:00
Xianjun Jiao	517e5abeb0	update figures to more presise status	2019-12-24 23:35:44 +01:00
Xianjun Jiao	3fa79e43d4	update figures to more presise status	2019-12-24 23:21:02 +01:00
Jiao Xianjun	0669334ca5	Update README.md	2019-12-23 09:55:20 +01:00
Jiao Xianjun	38f76c0177	Update README.md	2019-12-21 08:28:12 +01:00
Jiao Xianjun	7750643c45	Update README.md	2019-12-20 17:34:57 +01:00
Jiao Xianjun	1bbbbdc7f1	Update README.md	2019-12-20 17:31:07 +01:00
Jiao Xianjun	a20313b892	Update README.md	2019-12-20 17:27:52 +01:00
Jiao Xianjun	d288774fd4	Merge pull request #3 from weiliu1011/patch-4 ... Update README.md	2019-12-20 17:23:45 +01:00
Jiao Xianjun	1e3dcbe15d	Merge pull request #2 from weiliu1011/patch-3 ... minor fix	2019-12-20 17:21:28 +01:00
weiliu1011	62591d266a	Update README.md	2019-12-20 11:25:22 +01:00
weiliu1011	6a6fa9b48f	minor fix	2019-12-20 10:50:59 +01:00
Jiao Xianjun	c017e30599	Update README.md	2019-12-19 20:06:47 +01:00
Xianjun Jiao	20101e8202	update the detailed architecture figure	2019-12-19 09:10:24 +01:00
Xianjun Jiao	03cffd2a57	update the detailed architecture figure	2019-12-19 09:07:28 +01:00
Xianjun Jiao	08d06a7637	update the detailed architecture figure	2019-12-19 08:47:29 +01:00
Jiao Xianjun	4f977aa976	Update README.md	2019-12-18 20:36:15 +01:00
Jiao Xianjun	836d8a87ca	Update README.md	2019-12-18 08:22:07 +01:00
Jiao Xianjun	c3d9cd01f2	Update README.md	2019-12-17 16:51:19 +01:00
Jiao Xianjun	2309afd47c	add debug section	2019-12-13 09:51:51 +01:00
Jiao Xianjun	596eeae93c	Merge pull request #1 from weiliu1011/patch-2 ... typo fix README.md	2019-12-12 16:20:10 +01:00
weiliu1011	9a60a09840	Update README.md	2019-12-12 16:17:46 +01:00
Jiao Xianjun	ffe9541b4b	update README	2019-12-12 12:18:19 +01:00
Jiao Xianjun	10d539bee3	update document	2019-12-12 12:16:06 +01:00
Jiao Xianjun	5f436b3c82	update document	2019-12-12 10:10:10 +01:00
Jiao Xianjun	da62eb45a3	Fix a typo	2019-12-11 22:59:28 +01:00
Jiao Xianjun	5ae382e00b	udpate xilinx vivado version information	2019-12-11 14:36:56 +01:00
Jiao Xianjun	86bab9c1d6	fix/ease some steps. add content about ad9364/fmcomms2	2019-12-11 11:29:37 +01:00
Jiao Xianjun	a766ca2960	Update README.md	2019-12-10 18:43:51 +01:00
Jiao Xianjun	9b4c03062a	update video link to IDLabResearch youtube channel.	2019-12-10 18:27:28 +01:00
Jiao Xianjun	9e8d5e4ae1	add ftp setup section to README	2019-12-10 17:59:19 +01:00
Jiao Xianjun	96be0adb57	add necessary step in README	2019-12-10 15:46:33 +01:00
Jiao Xianjun	b3df431c67	Update .gitmodules	2019-12-10 15:44:01 +01:00
Jiao Xianjun	eb2476556a	update necessary links in README	2019-12-10 15:04:17 +01:00
Xianjun Jiao	14124d7306	add necessary external source code as submodule	2019-12-10 14:59:24 +01:00
Xianjun Jiao	2ee6717882	initial commit	2019-12-10 14:03:47 +01:00
imoerman	0df4ca4da2	Initial commit	2019-11-08 12:07:21 +01:00