13 Commits

Author	SHA1	Message	Date
Jiao Xianjun	2099dc84e8	Update build_zynqmp_boot_bin.sh	2021-02-03 15:46:02 +01:00
Jiao Xianjun	3b2784d451	Update build_boot_bin.sh	2021-02-03 15:45:40 +01:00
Lina Ceballos	a6085186d9	adding license and copyright headers	2021-01-20 13:30:12 +01:00
Xianjun Jiao	9634f24ef2	improve the kernel build procedure	2020-12-16 15:37:29 +01:00
Xianjun Jiao	5deb8d18f6	sync internal	2020-12-14 13:32:15 +01:00
Xianjun Jiao	f71252c537	iq capture feature	2020-10-19 10:13:51 +02:00
Xianjun Jiao	22dd0cc486	the side channel (timestamp, frequency offset, CSI, equalizer) feature	2020-10-08 15:07:57 +02:00
Xianjun Jiao	0a92505df2	add recent update: ... 1. add git revision software register 7 to DRV_XPU module (not FPGA XPU module) 2. fix the print of hdr->seq_ctrl in sdr.c 3. add ht_flag display to sdr.c 4. remove the sysid from devicetree because new we have our own git revision read back solution in FPGA (XPU register 63) and driver (the sotware register 7 of drv_xpu) 5. add sudo to update_sdcard.sh to make the image generation without SD card in the test-bed easier	2020-09-04 10:57:04 +02:00
Xianjun Jiao	8a6507ded8	add dtb. because they will not be changed frequently	2020-07-01 09:40:33 +02:00
Xianjun Jiao	febc5adf73	prepare upgrade	2020-04-27 09:37:04 +02:00
Xianjun Jiao	b73660ad79	prepare for release	2020-03-04 19:39:12 +01:00
Xianjun Jiao	89e3e0fbda	add support of adrv9361z7035 SOM	2020-01-15 18:14:50 +01:00
Xianjun Jiao	2ee6717882	initial commit	2019-12-10 14:03:47 +01:00