Lina Ceballos
a6085186d9
adding license and copyright headers
2021-01-20 13:30:12 +01:00
Xianjun Jiao
aa239344c1
use a better cca rssi threshold in sdr.c
2020-12-17 16:48:56 +01:00
Xianjun Jiao
5deb8d18f6
sync internal
2020-12-14 13:32:15 +01:00
mmehari
b6d7171315
sdr driver update for 80211n
2020-11-05 18:22:24 +01:00
Xianjun Jiao
22dd0cc486
the side channel (timestamp, frequency offset, CSI, equalizer) feature
2020-10-08 15:07:57 +02:00
Xianjun Jiao
0a92505df2
add recent update:
...
1. add git revision software register 7 to DRV_XPU module (not FPGA XPU module)
2. fix the print of hdr->seq_ctrl in sdr.c
3. add ht_flag display to sdr.c
4. remove the sysid from devicetree because new we have our own git revision read back solution in FPGA (XPU register 63) and driver (the sotware register 7 of drv_xpu)
5. add sudo to update_sdcard.sh to make the image generation without SD card in the test-bed easier
2020-09-04 10:57:04 +02:00
Xianjun Jiao
838a9007cf
update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing
2020-06-12 10:50:34 +02:00
Xianjun Jiao
febc5adf73
prepare upgrade
2020-04-27 09:37:04 +02:00
Xianjun Jiao
75042a3073
fix the tsf warning in sdr.c and sdrctl
2020-03-06 14:05:47 +01:00
Xianjun Jiao
e63d1ec300
Jetmir: add tsf set command to sdrctl
2020-03-05 08:50:41 +01:00
Xianjun Jiao
b73660ad79
prepare for release
2020-03-04 19:39:12 +01:00
Xianjun Jiao
2a1e074623
fix the potential memory access over boundary issue of openwifi_rx_interrupt and make necessary configuration for new FPGA that tx sending out I/Q immediately after tx_start which achieves 10us SIFS in 2.4GHz
2020-01-07 14:17:08 +01:00
Xianjun Jiao
2054f92c88
Fix the bug for monitor mode in driver sdr.c openwifi_configure_filter() function. Seems like monitor mode will create and use a new virtual interface, so priv-vif[0] is not valid anymore when monitor mode start and call openwifi_configure_filter()
2020-01-03 18:53:21 +01:00
Xianjun Jiao
2ee6717882
initial commit
2019-12-10 14:03:47 +01:00
