7 Commits

Author	SHA1	Message	Date
Jiao Xianjun	9e7be83fb0	Update xpu.c	2021-02-03 15:45:09 +01:00
Lina Ceballos	a6085186d9	adding license and copyright headers	2021-01-20 13:30:12 +01:00
Xianjun Jiao	5deb8d18f6	sync internal	2020-12-14 13:32:15 +01:00
Xianjun Jiao	838a9007cf	update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing	2020-06-12 10:50:34 +02:00
Xianjun Jiao	febc5adf73	prepare upgrade	2020-04-27 09:37:04 +02:00
Xianjun Jiao	2a1e074623	fix the potential memory access over boundary issue of openwifi_rx_interrupt and make necessary configuration for new FPGA that tx sending out I/Q immediately after tx_start which achieves 10us SIFS in 2.4GHz	2020-01-07 14:17:08 +01:00
Xianjun Jiao	2ee6717882	initial commit	2019-12-10 14:03:47 +01:00