Commit Graph

26 Commits

Author SHA1 Message Date
Xianjun Jiao
68314a4614 Add the missing rf_reg_val in priv 2022-03-28 14:57:49 +02:00
Xianjun Jiao
56203843f5 Add runtime tx/rx antenna switch support to driver 2022-03-28 14:49:15 +02:00
Xianjun Jiao
11d048d944 Re-structure/define drv reg idx. Add (drv) RF reg 2022-03-28 14:18:35 +02:00
Xianjun Jiao
d3ce582a3d Add the missing sdrctl reg category 2022-03-28 14:16:57 +02:00
Xianjun Jiao
b196f496df Add priv->actual_tx_lo preparing for further tx/rx related setting 2022-03-28 14:14:49 +02:00
Xianjun Jiao
2ae501ca2e Disable TID in sdr.c:
By default the TID is disabled in FPGA, because we currently try to TX and RX traffic for all TIDs. So, the TID related operations in sdr.c are removed.
2022-03-28 14:02:23 +02:00
Xianjun Jiao
0b4b8cc75d Add all Europe 5GHz channel support into driver 2022-03-28 13:58:05 +02:00
Xianjun Jiao
6a9949ee81 Replace some constants of number of NIC by MAX_NUM_VIF 2022-03-28 13:56:19 +02:00
mmehari
385339ab4b tx_interrupt if/else optimization 2022-01-06 15:11:05 +01:00
mmehari
0c0d5d827e use FPGA fifo count registers instead of software queue_cnt 2022-01-06 15:07:50 +01:00
mmehari
f738aefa50 A-MPDU tx aggregation support 2022-01-06 14:42:01 +01:00
mmehari
261bb9eef7 A-MPDU rx aggregation support 2022-01-06 14:13:24 +01:00
Jiao Xianjun
72c90e5e32
Merge pull request #104 from open-sdr/fix_large_ping_delay_igent
Fix the issue of iGent env related big ping delay:
2021-10-13 09:32:21 +02:00
Xianjun Jiao
109b1cfd3a Fix the issue of iGent env related big ping delay:
1. The issue only happens at zcu102 side, when it is tested as AP together with zedboard
2. The issue does not happen when zcu102 is client and zedboard is AP
3. The issue (most likely) does not happen in places other than iGent (like Pablo home)
4. Sometimes it does happen at my home when I test zcu102 as AP together with COTS WiFi
5. Indeed seems like the environment related. Guess some quick small packets in the environment quickly flush/round-up/mess-up the rx dma cyclic buffer, and the rx interrupt internal static variable target_buf_idx_old loses track of the background automatic rx dma cyclic buffer
6. The fix is for all board types (zcu102, zedboard, 7035, etc)
7. The driver compiling make_all.sh script generates USE_NEW_RX_INTERRUPT macro to pre_def.h to enable the new code (while keeping the old code). You can use the script as before.
8. The logic of the fix is that exhaustive search all the rx dma cyclic buffer in rx interrupt to get packet to Linux in the first place.
2021-09-29 16:52:45 +02:00
Xianjun Jiao
8598d2949d Use drv_xpu register 0 for LBT threshold setting. 0 will enable FPGA threshold auto setting by ad9361_rf_set_channel() in sdr.c. Other value will set static threshold (that value) to FPGA 2021-09-28 21:52:31 +02:00
luz paz
b1dd94e387 Fix various typos
Found via codespell v2.1.dev0  
`codespell -q 3 -L ans,filp,fils,hsi`
2021-02-04 20:41:51 +01:00
Jiao Xianjun
55c2866f7c
Merge pull request #54 from lnceballosz/master
NGI0 - Updating licensing aspects according REUSE
2021-02-03 16:14:49 +01:00
Jiao Xianjun
d8d76f8862
Update sdr.h 2021-02-03 15:40:16 +01:00
Lina Ceballos
a6085186d9 adding license and copyright headers 2021-01-20 13:30:12 +01:00
mmehari
6e3730c0c1 Linux queue waking/sleeping decision update: LARGE FPGA models were using small MAX_NUM_DMA_SYMBOL but now is based on /proc/device-tree/model information 2020-12-29 21:33:36 +01:00
mmehari
b6d7171315 sdr driver update for 80211n 2020-11-05 18:22:24 +01:00
Xianjun Jiao
22dd0cc486 the side channel (timestamp, frequency offset, CSI, equalizer) feature 2020-10-08 15:07:57 +02:00
Xianjun Jiao
0a92505df2 add recent update:
1. add git revision software register 7 to DRV_XPU module (not FPGA XPU module)
2. fix the print of hdr->seq_ctrl in sdr.c
3. add ht_flag display to sdr.c
4. remove the sysid from devicetree because new we have our own git revision read back solution in FPGA (XPU register 63) and driver (the sotware register 7 of drv_xpu)
5. add sudo to update_sdcard.sh to make the image generation without SD card in the test-bed easier
2020-09-04 10:57:04 +02:00
Xianjun Jiao
838a9007cf update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing 2020-06-12 10:50:34 +02:00
Xianjun Jiao
febc5adf73 prepare upgrade 2020-04-27 09:37:04 +02:00
Xianjun Jiao
2ee6717882 initial commit 2019-12-10 14:03:47 +01:00