openofdm/docs/source/index.rst

: Synthesizable, Modular Verilog Implementation of 802.11 OFDM Decoder

is a open source Verilog implementation of 802.11 OFDM decoder. Highlights are:

• Supports 802.11a/g (all bit rates) and 802.11n (20MHz BW, MCS 0 - 7)
• Modular design, easy to extend
• Fully synthesizable, tested on USRP N210

overview detection freq_offset sync_long eq decode sig setting verilog usrp