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85b1adbec7
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bug fix: increase phase calculation delay by 1 CLK
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2022-01-04 22:22:00 +01:00 |
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36c738fe98
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phase estimation update: quadrant quantization from 256 slices -> 512 slices
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2022-01-04 22:15:16 +01:00 |
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82d2d456e5
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keep significant bits while performing division during phase calculation
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2022-01-04 22:11:50 +01:00 |
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d9649eb614
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phase register size reduction: 32bit -> 16bit
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2022-01-04 22:10:36 +01:00 |
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d7f5806790
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fix the atan_addr overflow issue (phase.v)
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2020-08-29 14:48:38 +02:00 |
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47577f7099
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fix comment
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2017-04-14 11:00:12 -04:00 |
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9edf1899bd
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verilog init
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2017-04-03 12:52:03 -04:00 |
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