output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux

openofdm_rx_side_ch_sim_ultra_scale.tcl

@@ -0,0 +1,763 @@
+#*****************************************************************************************
+# 
+# By xianjun.jiao@imec.be; wei.liu@imec.be
+# 
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#
+#*****************************************************************************************
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir [file dirname [info script]]
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set project_name "openofdm_rx_side_ch_sim_ultra_scale"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set project_name $::user_project_name
+}
+
+variable script_file
+set script_file "openofdm_rx_side_ch_sim_ultra_scale.tcl"
+
+# Help information for this script
+proc help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < [llength $::argc]} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set project_name [lindex $::argv $i] }
+      "--help"         { help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set src_dir "[file normalize "$origin_dir/verilog"]"
+
+# Create project
+create_project ${project_name} ./${project_name} -part xczu9eg-ffvb1156-2-e
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Reconstruct message rules
+# None
+
+# Set project properties
+set obj [current_project]
+set_property -name "board_connections" -value "" -objects $obj
+set_property -name "board_part" -value "xilinx.com:zcu102:part0:3.1" -objects $obj
+set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/activehdl" -objects $obj
+set_property -name "compxlib.funcsim" -value "1" -objects $obj
+set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/ies" -objects $obj
+set_property -name "compxlib.modelsim_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/modelsim" -objects $obj
+set_property -name "compxlib.overwrite_libs" -value "0" -objects $obj
+set_property -name "compxlib.questa_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/questa" -objects $obj
+set_property -name "compxlib.riviera_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/riviera" -objects $obj
+set_property -name "compxlib.timesim" -value "1" -objects $obj
+set_property -name "compxlib.vcs_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/vcs" -objects $obj
+set_property -name "compxlib.xsim_compiled_library_dir" -value "" -objects $obj
+set_property -name "corecontainer.enable" -value "0" -objects $obj
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "dsa.num_compute_units" -value "60" -objects $obj
+set_property -name "dsa.rom.debug_type" -value "0" -objects $obj
+set_property -name "dsa.rom.prom_type" -value "0" -objects $obj
+set_property -name "enable_optional_runs_sta" -value "0" -objects $obj
+set_property -name "generate_ip_upgrade_log" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_interface_inference_priority" -value "" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${project_name}.cache/ip" -objects $obj
+set_property -name "project_type" -value "Default" -objects $obj
+set_property -name "pr_flow" -value "0" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "sim.use_ip_compiled_libs" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "source_mgmt_mode" -value "All" -objects $obj
+set_property -name "target_language" -value "Verilog" -objects $obj
+set_property -name "target_simulator" -value "XSim" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_MEMORY" -objects $obj
+set_property -name "xsim.array_display_limit" -value "1024" -objects $obj
+set_property -name "xsim.radix" -value "hex" -objects $obj
+set_property -name "xsim.time_unit" -value "ns" -objects $obj
+set_property -name "xsim.trace_limit" -value "65536" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+set_property "ip_repo_paths" "[file normalize "$origin_dir/verilog/coregen/div_gen_new_ip_core_zynquplus"]" $obj
+
+# Rebuild user ip_repo's index before adding any source files
+update_ip_catalog -rebuild
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/Xilinx/zynquplus/complex_multiplier/complex_multiplier.xci"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/Xilinx/zynquplus/atan_lut/atan_lut.xci"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/bits_to_bytes.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/calc_mean.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/complex_mult.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/complex_to_mag.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/complex_to_mag_sq.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/crc32.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/deinterleave.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/delayT.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/delay_sample.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/common_defs.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/demodulate.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/descramble.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/divider.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/dot11.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/equalizer.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/ht_sig_crc.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/moving_avg.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/ofdm_decoder.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/openofdm_rx_s_axi.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/phase.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/usrp2/ram_2port.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/rotate.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/stage_mult.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/sync_long.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/sync_short.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/openofdm_rx.v"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/Xilinx/zynquplus/deinter_lut/deinter_lut.coe"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/Xilinx/zynquplus/atan_lut/atan_lut.coe"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/Xilinx/zynquplus/rot_lut/rot_lut.coe"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/Xilinx/zynquplus/viterbi/viterbi_v7_0.xci"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/Xilinx/zynquplus/deinter_lut/deinter_lut.xci"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen_div_gen_0_0/div_gen_div_gen_0_0.xci"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen_xlslice_0_0/div_gen_xlslice_0_0.xci"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/Xilinx/zynquplus/xfft/xfft_v9.xci"] \
+ [file normalize "${origin_dir}/../openofdminternal/verilog/Xilinx/zynquplus/rot_lut/rot_lut.xci"] \
+ [file normalize "${origin_dir}/../openwifi-hw/ip/xpu/src/phy_rx_parse.v"] \
+ [file normalize "${origin_dir}/../openwifi-hw/ip/side_ch/src/side_ch_control.v"] \
+ [file normalize "${origin_dir}/../openwifi-hw/ip/side_ch/src/side_ch_m_axis.v"] \
+ [file normalize "${origin_dir}/../openwifi-hw/ip_repo/ultra_scale/fifo64_1clk_dep4k/src/fifo64_1clk_dep4k_fifo_generator_0_0/fifo64_1clk_dep4k_fifo_generator_0_0.xci"]\
+ [file normalize "${origin_dir}/../openwifi-hw/ip_repo/ultra_scale/fifo64_1clk_dep4k/src/fifo64_1clk_dep4k.v"]\
+]
+# If you want to make a copy of the file to new src folder, use following command
+# set imported_files [import_files -fileset sources_1 $files]
+# If you want to keep the files remote, use the following command
+# set added_files [add_files -fileset sources_1 $files]
+add_files -norecurse -fileset $obj $files
+
+# #Set 'sources_1' fileset file properties for remote files
+#set file "$origin_dir/verilog/coregen/div_gen_v3_0.ngc"
+#set file [file normalize $file]
+#set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+#set_property -name "file_type" -value "NGC" -objects $file_obj
+
+set file "openofdm_rx_s_axi.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "0" -objects $file_obj
+
+set file "openofdm_rx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "0" -objects $file_obj
+
+
+# Set 'sources_1' fileset file properties for local files
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "openofdm_rx" -objects $obj
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Empty (no sources present)
+
+
+# Create constraints ! 
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+
+# Create runs 
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+set files [list \
+ "[file normalize "$origin_dir/verilog/dot11_side_ch_tb.v"]"
+]
+add_files -norecurse -fileset $obj $files
+# Empty (no sources present)
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "32bit" -value "0" -objects $obj
+set_property -name "generic" -value "" -objects $obj
+set_property -name "include_dirs" -value "" -objects $obj
+set_property -name "incremental" -value "1" -objects $obj
+set_property -name "name" -value "sim_1" -objects $obj
+set_property -name "nl.cell" -value "" -objects $obj
+set_property -name "nl.incl_unisim_models" -value "0" -objects $obj
+set_property -name "nl.process_corner" -value "slow" -objects $obj
+set_property -name "nl.rename_top" -value "" -objects $obj
+set_property -name "nl.sdf_anno" -value "1" -objects $obj
+set_property -name "nl.write_all_overrides" -value "0" -objects $obj
+set_property -name "source_set" -value "sources_1" -objects $obj
+set_property -name "top" -value "dot11_side_ch_tb" -objects $obj
+set_property -name "transport_int_delay" -value "0" -objects $obj
+set_property -name "transport_path_delay" -value "0" -objects $obj
+set_property -name "verilog_define" -value "" -objects $obj
+set_property -name "verilog_uppercase" -value "0" -objects $obj
+set_property -name "xelab.dll" -value "0" -objects $obj
+set_property -name "xsim.compile.tcl.pre" -value "" -objects $obj
+set_property -name "xsim.compile.xvhdl.more_options" -value "" -objects $obj
+set_property -name "xsim.compile.xvhdl.nosort" -value "1" -objects $obj
+set_property -name "xsim.compile.xvhdl.relax" -value "1" -objects $obj
+set_property -name "xsim.compile.xvlog.more_options" -value "" -objects $obj
+set_property -name "xsim.compile.xvlog.nosort" -value "1" -objects $obj
+set_property -name "xsim.compile.xvlog.relax" -value "1" -objects $obj
+set_property -name "xsim.elaborate.debug_level" -value "typical" -objects $obj
+set_property -name "xsim.elaborate.load_glbl" -value "1" -objects $obj
+set_property -name "xsim.elaborate.mt_level" -value "auto" -objects $obj
+set_property -name "xsim.elaborate.rangecheck" -value "0" -objects $obj
+set_property -name "xsim.elaborate.relax" -value "1" -objects $obj
+set_property -name "xsim.elaborate.sdf_delay" -value "sdfmax" -objects $obj
+set_property -name "xsim.elaborate.snapshot" -value "" -objects $obj
+set_property -name "xsim.elaborate.xelab.more_options" -value "" -objects $obj
+set_property -name "xsim.simulate.custom_tcl" -value "" -objects $obj
+set_property -name "xsim.simulate.log_all_signals" -value "0" -objects $obj
+set_property -name "xsim.simulate.runtime" -value "1000ns" -objects $obj
+set_property -name "xsim.simulate.saif" -value "" -objects $obj
+set_property -name "xsim.simulate.saif_all_signals" -value "0" -objects $obj
+set_property -name "xsim.simulate.saif_scope" -value "" -objects $obj
+set_property -name "xsim.simulate.tcl.post" -value "" -objects $obj
+set_property -name "xsim.simulate.wdb" -value "" -objects $obj
+set_property -name "xsim.simulate.xsim.more_options" -value "" -objects $obj
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.pblocks" -value "" -objects $obj
+set_property -name "options.cells" -value "" -objects $obj
+set_property -name "options.slr" -value "0" -objects $obj
+set_property -name "options.packthru" -value "0" -objects $obj
+set_property -name "options.hierarchical" -value "0" -objects $obj
+set_property -name "options.hierarchical_depth" -value "" -objects $obj
+set_property -name "options.hierarchical_percentages" -value "0" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+set obj [get_runs synth_1]
+set_property -name "constrset" -value "constrs_1" -objects $obj
+set_property -name "description" -value "Vivado Synthesis Defaults" -objects $obj
+set_property -name "flow" -value "Vivado Synthesis 2018" -objects $obj
+set_property -name "name" -value "synth_1" -objects $obj
+set_property -name "needs_refresh" -value "0" -objects $obj
+set_property -name "srcset" -value "sources_1" -objects $obj
+# set_property -name "incremental_checkpoint" -value "" -objects $obj
+set_property -name "include_in_archive" -value "1" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+set_property -name "steps.synth_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.synth_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.synth_design.args.flatten_hierarchy" -value "rebuilt" -objects $obj
+set_property -name "steps.synth_design.args.gated_clock_conversion" -value "off" -objects $obj
+set_property -name "steps.synth_design.args.bufg" -value "12" -objects $obj
+set_property -name "steps.synth_design.args.fanout_limit" -value "10000" -objects $obj
+set_property -name "steps.synth_design.args.directive" -value "Default" -objects $obj
+set_property -name "steps.synth_design.args.retiming" -value "0" -objects $obj
+set_property -name "steps.synth_design.args.fsm_extraction" -value "auto" -objects $obj
+set_property -name "steps.synth_design.args.keep_equivalent_registers" -value "0" -objects $obj
+set_property -name "steps.synth_design.args.resource_sharing" -value "auto" -objects $obj
+set_property -name "steps.synth_design.args.control_set_opt_threshold" -value "auto" -objects $obj
+set_property -name "steps.synth_design.args.no_lc" -value "0" -objects $obj
+set_property -name "steps.synth_design.args.no_srlextract" -value "0" -objects $obj
+set_property -name "steps.synth_design.args.shreg_min_size" -value "3" -objects $obj
+set_property -name "steps.synth_design.args.max_bram" -value "-1" -objects $obj
+set_property -name "steps.synth_design.args.max_uram" -value "-1" -objects $obj
+set_property -name "steps.synth_design.args.max_dsp" -value "-1" -objects $obj
+set_property -name "steps.synth_design.args.max_bram_cascade_height" -value "-1" -objects $obj
+set_property -name "steps.synth_design.args.max_uram_cascade_height" -value "-1" -objects $obj
+set_property -name "steps.synth_design.args.cascade_dsp" -value "auto" -objects $obj
+set_property -name "steps.synth_design.args.assert" -value "0" -objects $obj
+set_property -name "steps.synth_design.args.more options" -value "" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2018" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.upgrade_cw" -value "0" -objects $obj
+set_property -name "options.checks" -value "" -objects $obj
+set_property -name "options.ruledecks" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.pblocks" -value "" -objects $obj
+set_property -name "options.cells" -value "" -objects $obj
+set_property -name "options.slr" -value "0" -objects $obj
+set_property -name "options.packthru" -value "0" -objects $obj
+set_property -name "options.hierarchical" -value "0" -objects $obj
+set_property -name "options.hierarchical_depth" -value "" -objects $obj
+set_property -name "options.hierarchical_percentages" -value "0" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.verbose" -value "1" -objects $obj
+set_property -name "options.cells" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.cells" -value "" -objects $obj
+set_property -name "options.hierarchical" -value "0" -objects $obj
+set_property -name "options.hierarchical_depth" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.cells" -value "" -objects $obj
+set_property -name "options.hierarchical" -value "0" -objects $obj
+set_property -name "options.hierarchical_depth" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.upgrade_cw" -value "0" -objects $obj
+set_property -name "options.checks" -value "" -objects $obj
+set_property -name "options.ruledecks" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.checks" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.advisory" -value "0" -objects $obj
+set_property -name "options.xpe" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.of_objects" -value "" -objects $obj
+set_property -name "options.route_type" -value "" -objects $obj
+set_property -name "options.list_all_nets" -value "0" -objects $obj
+set_property -name "options.show_all" -value "0" -objects $obj
+set_property -name "options.has_routing" -value "0" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.cells" -value "" -objects $obj
+set_property -name "options.hierarchical" -value "0" -objects $obj
+set_property -name "options.hierarchical_depth" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.write_xdc" -value "0" -objects $obj
+set_property -name "options.clock_roots_only" -value "0" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "constrset" -value "constrs_1" -objects $obj
+set_property -name "description" -value "Default settings for Implementation." -objects $obj
+set_property -name "flow" -value "Vivado Implementation 2018" -objects $obj
+set_property -name "name" -value "impl_1" -objects $obj
+set_property -name "needs_refresh" -value "0" -objects $obj
+set_property -name "pr_configuration" -value "" -objects $obj
+set_property -name "srcset" -value "sources_1" -objects $obj
+# set_property -name "incremental_checkpoint" -value "" -objects $obj
+set_property -name "include_in_archive" -value "1" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.opt_design.is_enabled" -value "1" -objects $obj
+set_property -name "steps.opt_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.opt_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.opt_design.args.verbose" -value "0" -objects $obj
+set_property -name "steps.opt_design.args.directive" -value "Default" -objects $obj
+set_property -name "steps.opt_design.args.more options" -value "" -objects $obj
+set_property -name "steps.power_opt_design.is_enabled" -value "0" -objects $obj
+set_property -name "steps.power_opt_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.power_opt_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.power_opt_design.args.more options" -value "" -objects $obj
+set_property -name "steps.place_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.place_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.place_design.args.directive" -value "Default" -objects $obj
+set_property -name "steps.place_design.args.more options" -value "" -objects $obj
+set_property -name "steps.post_place_power_opt_design.is_enabled" -value "0" -objects $obj
+set_property -name "steps.post_place_power_opt_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.post_place_power_opt_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.post_place_power_opt_design.args.more options" -value "" -objects $obj
+set_property -name "steps.phys_opt_design.is_enabled" -value "0" -objects $obj
+set_property -name "steps.phys_opt_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.phys_opt_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.phys_opt_design.args.directive" -value "Default" -objects $obj
+set_property -name "steps.phys_opt_design.args.more options" -value "" -objects $obj
+set_property -name "steps.route_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.route_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.route_design.args.directive" -value "Default" -objects $obj
+set_property -name "steps.route_design.args.more options" -value "" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "0" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.args.directive" -value "Default" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.args.more options" -value "" -objects $obj
+set_property -name "steps.write_bitstream.tcl.pre" -value "" -objects $obj
+set_property -name "steps.write_bitstream.tcl.post" -value "" -objects $obj
+set_property -name "steps.write_bitstream.args.raw_bitfile" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.mask_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.no_binary_bitfile" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.bin_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.logic_location_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.more options" -value "" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:$project_name"

openofdm_rx_ultra_scale.tcl

@@ -2,9 +2,6 @@
 # 
 # By xianjun.jiao@imec.be; wei.liu@imec.be
 # 
-# Generated by Vivado on Mon Jan 21 11:32:41 +0100 2019
-# IP Build 2095745 on Tue Jan 30 17:13:15 MST 2018
-#
 # This file contains the Vivado Tcl commands for re-creating the project to the state*
 # when this script was generated. In order to re-create the project, please source this
 # file in the Vivado Tcl Shell.

testing_inputs/conducted/dot11a_48mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42_openwifi-1.txt

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verilog/dot11.v

@@ -43,9 +43,11 @@ module dot11 (
     /////////////////////////////////////////////////////////
     
     // decode status
+    // (* mark_debug = "true", DONT_TOUCH = "TRUE" *) 
     output reg [3:0] state,
     output reg [3:0] status_code,
     output state_changed,
+    output reg [31:0] state_history,
 
     // power trigger
     output power_trigger,
@@ -60,12 +62,14 @@ module dot11 (
     output long_preamble_detected,
     output [31:0] sync_long_out,
     output sync_long_out_strobe,
+    output wire signed [31:0] phase_offset_taken,
     output [2:0] sync_long_state,
 
     // equalizer
     output [31:0] equalizer_out,
     output equalizer_out_strobe,
     output [2:0] equalizer_state,
+    output wire ofdm_symbol_eq_out_pulse,
 
     // legacy signal info
     output reg legacy_sig_stb,
@@ -101,11 +105,36 @@ module dot11 (
     output conv_decoder_out_stb,
 
     output descramble_out,
-    output descramble_out_strobe
+    output descramble_out_strobe,
+
+    // for side channel
+    output wire [31:0] csi,
+    output wire csi_valid
 );
 
 `include "common_params.v"
 
+////////////////////////////////////////////////////////////////////////////////
+// extra info output to ease side info and viterbi state monitor
+////////////////////////////////////////////////////////////////////////////////
+reg  [2:0] equalizer_state_reg;
+
+assign ofdm_symbol_eq_out_pulse = (equalizer_state==4 && equalizer_state_reg==6);
+
+always @(posedge clock) begin
+    if (reset==1) begin
+        state_history <= 0;
+        equalizer_state_reg <= 0;
+    end else begin
+        equalizer_state_reg <= equalizer_state;
+        if (state_changed) begin
+            state_history[3:0] <= state;
+            state_history[31:4] <= state_history[27:0];
+        end 
+    end
+end
+////////////////////////////////////////////////////////////////////////////////
+
 
 ////////////////////////////////////////////////////////////////////////////////
 // Shared rotation LUT for sync_long and equalizer
@@ -128,7 +157,6 @@ rot_lut rot_lut_inst (
 ////////////////////////////////////////////////////////////////////////////////
 
 
-
 ////////////////////////////////////////////////////////////////////////////////
 // Shared phase module for sync_short and equalizer
 ////////////////////////////////////////////////////////////////////////////////
@@ -323,6 +351,7 @@ sync_long sync_long_inst (
     .metric(sync_long_metric),
     .metric_stb(sync_long_metric_stb),
     .long_preamble_detected(long_preamble_detected),
+    .phase_offset_taken(phase_offset_taken),
     .state(sync_long_state),
 
     .sample_out(sync_long_out),
@@ -338,6 +367,7 @@ equalizer equalizer_inst (
     .sample_in(sync_long_out),
     .sample_in_strobe(sync_long_out_strobe),
     .ht_next(ht_next),
+    .pkt_ht(pkt_ht),
 
     .phase_in_i(eq_phase_in_i),
     .phase_in_q(eq_phase_in_q),
@@ -352,7 +382,10 @@ equalizer equalizer_inst (
     .sample_out(equalizer_out),
     .sample_out_strobe(equalizer_out_strobe),
 
-    .state(equalizer_state)
+    .state(equalizer_state),
+
+    .csi(csi),
+    .csi_valid(csi_valid)
 );
 
 
@@ -480,6 +513,8 @@ always @(posedge clock) begin
 
         case(state)
             S_WAIT_POWER_TRIGGER: begin
+                pkt_begin <= 0;
+                pkt_ht <= 0;
                 crc_reset <= 0;
                 short_gi <= 0;
                 demod_is_ongoing <= 0;
@@ -623,7 +658,6 @@ always @(posedge clock) begin
                         pkt_header_valid <= 1;
                         pkt_header_valid_strobe <= 1;
                         pkt_begin <= 1;
-                        pkt_ht <= 0;
                         state <= S_DECODE_DATA;
                     end
                 end
@@ -661,7 +695,6 @@ always @(posedge clock) begin
                     pkt_header_valid <= 1;
                     pkt_header_valid_strobe <= 1;
                     pkt_begin <= 1;
-                    pkt_ht <= 0;
                     state <= S_DECODE_DATA;
                 end
             end

verilog/dot11_side_ch_tb.v

@@ -0,0 +1,590 @@
+`timescale 1ns/1ps
+
+module dot11_side_ch_tb;
+`include "common_params.v"
+
+localparam integer TSF_TIMER_WIDTH = 64; // according to 802.11 standard
+
+localparam integer GPIO_STATUS_WIDTH = 8;
+localparam integer RSSI_HALF_DB_WIDTH = 11;
+
+localparam integer ADC_PACK_DATA_WIDTH	= 64;
+localparam integer IQ_DATA_WIDTH	=     16;
+localparam integer RSSI_DATA_WIDTH	=     10;
+		
+localparam integer C_S00_AXI_DATA_WIDTH	= 32;
+localparam integer C_S00_AXI_ADDR_WIDTH	= 7;
+
+localparam integer C_S00_AXIS_TDATA_WIDTH	= 64;
+localparam integer C_M00_AXIS_TDATA_WIDTH	= 64;
+		
+localparam integer WAIT_COUNT_BITS = 5;
+localparam integer MAX_NUM_DMA_SYMBOL = 4096; // the fifo depth inside m_axis
+
+function integer clogb2 (input integer bit_depth);                                   
+    begin                                                                              
+    for(clogb2=0; bit_depth>0; clogb2=clogb2+1)                                      
+        bit_depth = bit_depth >> 1;                                                    
+    end                                                                                
+endfunction   
+
+localparam integer MAX_BIT_NUM_DMA_SYMBOL  = clogb2(MAX_NUM_DMA_SYMBOL);
+
+reg clock;
+reg reset;
+reg enable;
+
+reg [10:0] rssi_half_db;
+reg[31:0] sample_in;
+reg sample_in_strobe;
+reg [15:0] clk_count;
+
+wire [31:0] sync_short_metric;
+wire short_preamble_detected;
+wire power_trigger;
+
+wire [31:0] sync_long_out;
+wire sync_long_out_strobe;
+wire [31:0] sync_long_metric;
+wire sync_long_metric_stb;
+wire long_preamble_detected;
+
+wire [31:0] equalizer_out;
+wire equalizer_out_strobe;
+
+wire [5:0] demod_out;
+wire demod_out_strobe;
+
+wire [7:0] deinterleave_erase_out;
+wire deinterleave_erase_out_strobe;
+
+wire conv_decoder_out;
+wire conv_decoder_out_stb;
+
+wire descramble_out;
+wire descramble_out_strobe;
+
+wire [3:0] legacy_rate;
+wire legacy_sig_rsvd;
+wire [11:0] legacy_len;
+wire legacy_sig_parity;
+wire [5:0] legacy_sig_tail;
+wire legacy_sig_stb;
+reg signal_done;
+
+wire [3:0] dot11_state;
+
+wire pkt_header_valid;
+wire pkt_header_valid_strobe;
+wire [7:0] byte_out;
+wire byte_out_strobe;
+wire [15:0] byte_count_total;
+wire [15:0] byte_count;
+wire [15:0] pkt_len_total;
+wire [15:0] pkt_len;
+// wire [63:0] word_out;
+// wire word_out_strobe;
+
+wire demod_is_ongoing;
+wire ofdm_symbol_eq_out_pulse;
+wire ht_unsupport;
+wire [7:0] pkt_rate;
+wire [(32-1):0] csi;
+wire csi_valid;
+
+wire [31:0] FC_DI;
+wire FC_DI_valid;
+        
+wire [47:0] addr1;
+wire addr1_valid;
+wire [47:0] addr2;
+wire addr2_valid;
+wire [47:0] addr3;
+wire addr3_valid;
+
+wire m_axis_start_1trans;
+wire [63:0] data_to_ps;
+wire data_to_ps_valid;
+wire [12:0] m_axis_data_count;
+wire fulln_to_pl;
+wire M_AXIS_TVALID;
+wire M_AXIS_TLAST;
+
+reg slv_reg_wren_signal;
+reg [4:0] axi_awaddr_core;
+reg m_axis_start_ext_trigger;
+
+reg [3:0] num_eq;
+
+reg set_stb;
+reg [7:0] set_addr;
+reg [31:0] set_data;
+
+wire fcs_out_strobe, fcs_ok;
+
+integer addr;
+
+integer bb_sample_fd;
+integer power_trigger_fd;
+integer short_preamble_detected_fd;
+
+integer long_preamble_detected_fd;
+integer sync_long_metric_fd;
+integer sync_long_out_fd;
+
+integer equalizer_out_fd;
+
+integer demod_out_fd;
+integer deinterleave_erase_out_fd;
+integer conv_out_fd;
+integer descramble_out_fd;
+
+integer signal_fd;
+
+integer byte_out_fd;
+
+integer file_i, file_q, file_rssi_half_db, iq_sample_file;
+
+`define SPEED_100M // remove this to use 200M
+
+//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_ht_unsupport_openwifi.txt"
+//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_ht_sig_openwifi.txt"
+//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_sig_openwifi.txt"
+//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_openwifi.txt"
+// `define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_6.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
+// `define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_52mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
+// `define SAMPLE_FILE "../../../../../testing_inputs/radiated/dot11n_19.5mbps_openwifi.txt"
+//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_58.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
+// `define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_65mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt" 
+// `define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11a_48mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42_openwifi.txt"
+//`define SAMPLE_FILE "../../../../../testing_inputs/radiated/ack-ok-openwifi.txt"
+`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_mixed_for_side_ch_openwifi.txt"
+
+`define NUM_SAMPLE 18560
+
+//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/openofdm_tx/PL_100Bytes/54Mbps.txt"
+//`define NUM_SAMPLE 2048
+
+initial begin
+    $dumpfile("dot11.vcd");
+    $dumpvars;
+
+    slv_reg_wren_signal = 0;
+    axi_awaddr_core = 0;
+    m_axis_start_ext_trigger = 0;
+
+    clock = 0;
+    reset = 1;
+    enable = 0;
+    signal_done <= 0;
+
+    # 20 reset = 0;
+    enable = 1;
+
+    set_stb = 1;
+
+    # 20
+    // do not skip sample
+    set_addr = SR_SKIP_SAMPLE;
+    set_data = 0;
+
+    # 20 set_stb = 0;
+end
+
+integer file_open_trigger = 0;
+always @(posedge clock) begin
+    file_open_trigger = file_open_trigger + 1;
+    if (file_open_trigger==1) begin
+        iq_sample_file = $fopen(`SAMPLE_FILE, "r");
+
+        bb_sample_fd = $fopen("./sample_in.txt", "w");
+        power_trigger_fd = $fopen("./power_trigger.txt", "w");
+        short_preamble_detected_fd = $fopen("./short_preamble_detected.txt", "w");
+
+        sync_long_metric_fd = $fopen("./sync_long_metric.txt", "w");
+        long_preamble_detected_fd = $fopen("./sync_long_frame_detected.txt", "w");
+        sync_long_out_fd = $fopen("./sync_long_out.txt", "w");
+
+        equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
+
+        demod_out_fd = $fopen("./demod_out.txt", "w");
+        deinterleave_erase_out_fd = $fopen("./deinterleave_erase_out.txt", "w");
+        conv_out_fd = $fopen("./conv_out.txt", "w");
+        descramble_out_fd = $fopen("./descramble_out.txt", "w");
+
+        signal_fd = $fopen("./signal_out.txt", "w");
+
+        byte_out_fd = $fopen("./byte_out.txt", "w");
+    end
+end
+
+`ifdef SPEED_100M
+    always begin //100MHz
+        #5 clock = !clock;
+    end
+`else
+    always begin //200MHz
+        #2.5 clock = !clock;
+    end
+`endif
+
+always @(posedge clock) begin
+    if (reset) begin
+        sample_in <= 0;
+        clk_count <= 0;
+        sample_in_strobe <= 0;
+        addr <= 0;
+        
+        num_eq <= 5;
+    end else if (enable) begin
+        `ifdef SPEED_100M
+    	if (clk_count == 4) begin  // for 100M; 100/20 = 5
+    	`else
+        if (clk_count == 9) begin // for 200M; 200/20 = 10
+        `endif
+            sample_in_strobe <= 1;
+            //$fscanf(iq_sample_file, "%d %d %d", file_i, file_q, file_rssi_half_db);
+            $fscanf(iq_sample_file, "%d %d", file_i, file_q);
+            sample_in[15:0] <= file_q;
+            sample_in[31:16]<= file_i;
+            //rssi_half_db <= file_rssi_half_db;
+            rssi_half_db <= 0;
+            addr <= addr + 1;
+            clk_count <= 0;
+        end else begin
+            sample_in_strobe <= 0;
+            clk_count <= clk_count + 1;
+        end
+
+        if (short_preamble_detected) begin
+            num_eq <= num_eq + 3;
+        end
+        
+        if (legacy_sig_stb) begin
+        end
+
+        //if (sample_in_strobe && power_trigger) begin
+        if (sample_in_strobe) begin
+            $fwrite(bb_sample_fd, "%d %d %d\n", $time/2, $signed(sample_in[31:16]), $signed(sample_in[15:0]));
+            $fwrite(power_trigger_fd, "%d %d\n", $time/2, power_trigger);
+            $fwrite(short_preamble_detected_fd, "%d %d\n", $time/2, short_preamble_detected);
+
+            $fwrite(long_preamble_detected_fd, "%d %d\n", $time/2, long_preamble_detected);
+
+            $fflush(bb_sample_fd);
+            $fflush(power_trigger_fd);
+            $fflush(short_preamble_detected_fd);
+            $fflush(long_preamble_detected_fd);
+
+
+            if ((addr % 100) == 0) begin
+                $display("%d", addr);
+            end
+
+            if (addr == `NUM_SAMPLE) begin
+                $fclose(iq_sample_file);
+
+                $fclose(bb_sample_fd);
+                $fclose(power_trigger_fd);
+                $fclose(short_preamble_detected_fd);
+
+                $fclose(sync_long_metric_fd);
+                $fclose(long_preamble_detected_fd);
+                $fclose(sync_long_out_fd);
+
+                $fclose(equalizer_out_fd);
+
+                $fclose(demod_out_fd);
+                $fclose(deinterleave_erase_out_fd);
+                $fclose(conv_out_fd);
+                $fclose(descramble_out_fd);
+
+                $fclose(signal_fd);
+                $fclose(byte_out_fd);
+    
+                $finish;
+            end
+        end
+
+        if (sync_long_metric_stb) begin
+            $fwrite(sync_long_metric_fd, "%d %d\n", $time/2, sync_long_metric);
+            $fflush(sync_long_metric_fd);
+        end
+
+        if (sync_long_out_strobe) begin
+            $fwrite(sync_long_out_fd, "%d %d\n", $signed(sync_long_out[31:16]), $signed(sync_long_out[15:0]));
+            $fflush(sync_long_out_fd);
+        end
+
+        if (equalizer_out_strobe) begin
+            $fwrite(equalizer_out_fd, "%d %d\n", $signed(equalizer_out[31:16]), $signed(equalizer_out[15:0]));
+            $fflush(equalizer_out_fd);
+        end
+
+        if (legacy_sig_stb) begin
+            signal_done <= 1;
+            $fwrite(signal_fd, "%04b %b %012b %b %06b", legacy_rate, legacy_sig_rsvd, legacy_len, legacy_sig_parity, legacy_sig_tail);
+            $fflush(signal_fd);
+        end
+
+        if (dot11_state == S_DECODE_DATA && demod_out_strobe) begin
+            $fwrite(demod_out_fd, "%b %b %b %b %b %b\n",demod_out[0],demod_out[1],demod_out[2],demod_out[3],demod_out[4],demod_out[5]);
+            $fflush(demod_out_fd);
+        end
+
+        if (dot11_state == S_DECODE_DATA && deinterleave_erase_out_strobe) begin
+            $fwrite(deinterleave_erase_out_fd, "%b %b %b %b %b %b %b %b\n", deinterleave_erase_out[0], deinterleave_erase_out[1], deinterleave_erase_out[2],  deinterleave_erase_out[3], deinterleave_erase_out[4], deinterleave_erase_out[5], deinterleave_erase_out[6],  deinterleave_erase_out[7]);
+            $fflush(deinterleave_erase_out_fd);
+        end
+
+        if (dot11_state == S_DECODE_DATA && conv_decoder_out_stb) begin
+            $fwrite(conv_out_fd, "%b\n", conv_decoder_out);
+            $fflush(conv_out_fd);
+        end
+
+        if (dot11_state == S_DECODE_DATA && descramble_out_strobe) begin
+            $fwrite(descramble_out_fd, "%b\n", descramble_out);
+            $fflush(descramble_out_fd);
+        end
+
+        if (dot11_state == S_DECODE_DATA && byte_out_strobe) begin
+            $fwrite(byte_out_fd, "%02x\n", byte_out);
+            $fflush(byte_out_fd);
+        end
+
+    end
+end
+
+side_ch_control # (
+    .TSF_TIMER_WIDTH(TSF_TIMER_WIDTH), // according to 802.11 standard
+
+    .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
+    .IQ_DATA_WIDTH(IQ_DATA_WIDTH),
+    .C_S_AXIS_TDATA_WIDTH(C_S00_AXIS_TDATA_WIDTH),
+    .MAX_NUM_DMA_SYMBOL(MAX_NUM_DMA_SYMBOL),
+    .MAX_BIT_NUM_DMA_SYMBOL(MAX_BIT_NUM_DMA_SYMBOL)
+) side_ch_control_i (
+    .clk(clock),
+    .rstn(~reset),
+
+	// from pl
+    .tsf_runtime_val(64'd123456),
+    .demod_is_ongoing(demod_is_ongoing),
+    .ofdm_symbol_eq_out_pulse(ofdm_symbol_eq_out_pulse),
+    .ht_unsupport(ht_unsupport),
+    .pkt_rate(pkt_rate),
+    .pkt_len(pkt_len),
+    .csi(csi),
+    .csi_valid(csi_valid),
+    .equalizer(equalizer_out),
+    .equalizer_valid(equalizer_out_strobe),
+
+    .pkt_header_valid(pkt_header_valid),
+    .pkt_header_valid_strobe(pkt_header_valid_strobe),
+    .FC_DI(FC_DI),
+    .FC_DI_valid(FC_DI_valid),
+    .addr1(addr1),
+    .addr1_valid(addr1_valid),
+    .addr2(addr2),
+    .addr2_valid(addr2_valid),
+    .addr3(addr3),
+    .addr3_valid(addr3_valid),
+
+    .fcs_in_strobe(fcs_out_strobe),
+    .fcs_ok(fcs_ok),
+    .block_rx_dma_to_ps(),
+    .block_rx_dma_to_ps_valid(),
+
+	// from arm
+    .slv_reg_wren_signal(slv_reg_wren_signal), // to capture m axis num dma symbol write, so that auto trigger start
+    .axi_awaddr_core(axi_awaddr_core),
+    .addr1_target(32'd23343),
+    .match_cfg(1),
+    .num_eq({1'd0, num_eq[2:0]}),
+    .m_axis_start_mode(1),
+    .m_axis_start_ext_trigger(m_axis_start_ext_trigger),
+
+	// s_axis
+    .data_to_pl(),
+    .pl_ask_data(),
+    .s_axis_data_count(),
+    .emptyn_to_pl(),
+
+    .S_AXIS_TVALID(),
+    .S_AXIS_TLAST(),
+
+	// m_axis
+    .m_axis_start_1trans(m_axis_start_1trans),
+
+    .data_to_ps(data_to_ps),
+    .data_to_ps_valid(data_to_ps_valid),
+    .m_axis_data_count(m_axis_data_count),
+    .fulln_to_pl(fulln_to_pl),
+        
+    .M_AXIS_TVALID(M_AXIS_TVALID),
+    .M_AXIS_TLAST(M_AXIS_TLAST)
+);
+
+side_ch_m_axis # (
+    // .WAIT_COUNT_BITS(WAIT_COUNT_BITS),
+    .MAX_NUM_DMA_SYMBOL(MAX_NUM_DMA_SYMBOL),
+    .MAX_BIT_NUM_DMA_SYMBOL(MAX_BIT_NUM_DMA_SYMBOL),
+    .C_M_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH)
+) side_ch_m_axis_i (
+    .m_axis_endless_mode(0),
+    .M_AXIS_NUM_DMA_SYMBOL(3222-1),
+
+    .m_axis_start_1trans(m_axis_start_1trans),
+
+    .data_to_ps(data_to_ps),
+    .data_to_ps_valid(data_to_ps_valid),
+    .m_axis_data_count(m_axis_data_count),
+    .fulln_to_pl(fulln_to_pl),
+
+    .M_AXIS_ACLK(clock),
+    .M_AXIS_ARESETN( ~reset ),
+    .M_AXIS_TVALID(M_AXIS_TVALID),
+    .M_AXIS_TDATA(),
+    .M_AXIS_TSTRB(),
+    .M_AXIS_TLAST(M_AXIS_TLAST),
+    .M_AXIS_TREADY(1)		
+);
+
+phy_rx_parse phy_rx_parse_inst (
+    .clk(clock),
+    .rstn( ~reset ),
+
+    .ofdm_byte_index(byte_count),
+    .ofdm_byte(byte_out),
+    .ofdm_byte_valid(byte_out_strobe),
+
+    .FC_DI(FC_DI),
+    .FC_DI_valid(FC_DI_valid),
+        
+    .rx_addr(addr1),
+    .rx_addr_valid(addr1_valid),
+        
+    .dst_addr(addr2),
+    .dst_addr_valid(addr2_valid),
+        
+    .tx_addr(addr3),
+    .tx_addr_valid(addr3_valid),
+        
+    .SC(),
+    .SC_valid(),
+        
+    .src_addr(),
+    .src_addr_valid()
+);
+
+dot11 dot11_inst (
+    .clock(clock),
+    .enable(enable),
+    .reset(reset),
+
+    //.set_stb(set_stb),
+    //.set_addr(set_addr),
+    //.set_data(set_data),
+
+    .power_thres(11'd0),
+    .min_plateau(32'd100),
+
+    .rssi_half_db(rssi_half_db),
+    .sample_in(sample_in),
+    .sample_in_strobe(sample_in_strobe),
+    .soft_decoding(1'b1),
+
+    .demod_is_ongoing(demod_is_ongoing),
+    .pkt_begin(pkt_begin),
+    .pkt_ht(pkt_ht),
+    .pkt_header_valid(pkt_header_valid),
+    .pkt_header_valid_strobe(pkt_header_valid_strobe),
+    .ht_unsupport(ht_unsupport),
+    .pkt_rate(pkt_rate),
+    .pkt_len(pkt_len),
+    .pkt_len_total(pkt_len_total),
+    .byte_out_strobe(byte_out_strobe),
+    .byte_out(byte_out),
+    .byte_count_total(byte_count_total),
+    .byte_count(byte_count),
+    .fcs_out_strobe(fcs_out_strobe),
+    .fcs_ok(fcs_ok),
+
+    .state(dot11_state),
+    .status_code(status_code),
+    .state_changed(state_changed),
+    .state_history(state_history),
+
+    .power_trigger(power_trigger),
+
+    .short_preamble_detected(short_preamble_detected),
+    .phase_offset(phase_offset),
+
+    .sync_long_metric(sync_long_metric),
+    .sync_long_metric_stb(sync_long_metric_stb),
+    .long_preamble_detected(long_preamble_detected),
+    .sync_long_out(sync_long_out),
+    .sync_long_out_strobe(sync_long_out_strobe),
+    .sync_long_state(sync_long_state),
+
+    .equalizer_out(equalizer_out),
+    .equalizer_out_strobe(equalizer_out_strobe),
+    .equalizer_state(equalizer_state),
+    .ofdm_symbol_eq_out_pulse(ofdm_symbol_eq_out_pulse),
+
+    .legacy_sig_stb(legacy_sig_stb),
+    .legacy_rate(legacy_rate),
+    .legacy_sig_rsvd(legacy_sig_rsvd),
+    .legacy_len(legacy_len),
+    .legacy_sig_parity(legacy_sig_parity),
+    .legacy_sig_parity_ok(legacy_sig_parity_ok),
+    .legacy_sig_tail(legacy_sig_tail),
+
+    .ht_sig_stb(ht_sig_stb),
+    .ht_mcs(ht_mcs),
+    .ht_cbw(ht_cbw),
+    .ht_len(ht_len),
+    .ht_smoothing(ht_smoothing),
+    .ht_not_sounding(ht_not_sounding),
+    .ht_aggregation(ht_aggregation),
+    .ht_stbc(ht_stbc),
+    .ht_fec_coding(ht_fec_coding),
+    .ht_sgi(ht_sgi),
+    .ht_num_ext(ht_num_ext),
+    .ht_sig_crc_ok(ht_sig_crc_ok),
+
+    .demod_out(demod_out),
+    .demod_out_strobe(demod_out_strobe),
+
+    .deinterleave_erase_out(deinterleave_erase_out),
+    .deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
+
+    .conv_decoder_out(conv_decoder_out),
+    .conv_decoder_out_stb(conv_decoder_out_stb),
+
+    .csi(csi),
+    .csi_valid(csi_valid),
+
+    .descramble_out(descramble_out),
+    .descramble_out_strobe(descramble_out_strobe)
+);
+
+/*
+byte_to_word_fcs_sn_insert byte_to_word_fcs_sn_insert_inst (
+    .clk(clock),
+    .rstn((~reset)&(~pkt_header_valid_strobe)),
+
+    .byte_in(byte_out),
+    .byte_in_strobe(byte_out_strobe),
+    .byte_count(byte_count),
+    .num_byte(pkt_len),
+    .fcs_in_strobe(fcs_out_strobe),
+    .fcs_ok(fcs_ok),
+    .rx_pkt_sn_plus_one(0),
+
+    .word_out(word_out),
+    .word_out_strobe(word_out_strobe)
+);
+*/
+
+endmodule

verilog/dot11_tb.v

@@ -22,7 +22,6 @@ wire [31:0] sync_long_metric;
 wire sync_long_metric_stb;
 wire long_preamble_detected;
 
-
 wire [31:0] equalizer_out;
 wire equalizer_out_strobe;
 
@@ -85,16 +84,26 @@ integer signal_fd;
 
 integer byte_out_fd;
 
-
-
 integer file_i, file_q, file_rssi_half_db, iq_sample_file;
 
+//`define SPEED_100M // comment out this to use 200M
+
+//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_ht_unsupport_openwifi.txt"
+//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_ht_sig_openwifi.txt"
+//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_sig_openwifi.txt"
+`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_openwifi.txt"
+//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_6.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
+//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_52mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
+//`define SAMPLE_FILE "../../../../../testing_inputs/radiated/dot11n_19.5mbps_openwifi.txt"
+//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_58.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
 //`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_65mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt" 
 //`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11a_48mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42_openwifi.txt"
-//`define NUM_SAMPLE 4560
+//`define SAMPLE_FILE "../../../../../testing_inputs/radiated/ack-ok-openwifi.txt"
 
-`define SAMPLE_FILE "../../../../../testing_inputs/simulated/openofdm_tx/PL_100Bytes/54Mbps.txt"
+`define NUM_SAMPLE 8560
-`define NUM_SAMPLE 2048
+
+//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/openofdm_tx/PL_100Bytes/54Mbps.txt"
+//`define NUM_SAMPLE 2048
 
 initial begin
     $dumpfile("dot11.vcd");
@@ -145,15 +154,15 @@ always @(posedge clock) begin
     end
 end
 
-always begin //100MHz
+`ifdef SPEED_100M
-    #5 clock = !clock;
+    always begin //100MHz
-end
+        #5 clock = !clock;
-
+    end
-/*
+`else
-always begin //200MHz
+    always begin //200MHz
-    #2.5 clock = !clock;
+        #2.5 clock = !clock;
-end
+    end
-*/
+`endif
 
 always @(posedge clock) begin
     if (reset) begin
@@ -162,8 +171,11 @@ always @(posedge clock) begin
         sample_in_strobe <= 0;
         addr <= 0;
     end else if (enable) begin
-	if (clk_count == 4) begin  // for 100M; 100/20 = 5
+        `ifdef SPEED_100M
-        // if (clk_count == 9) begin // for 200M; 200/20 = 10
+    	if (clk_count == 4) begin  // for 100M; 100/20 = 5
+    	`else
+        if (clk_count == 9) begin // for 200M; 200/20 = 10
+        `endif
             sample_in_strobe <= 1;
             //$fscanf(iq_sample_file, "%d %d %d", file_i, file_q, file_rssi_half_db);
             $fscanf(iq_sample_file, "%d %d", file_i, file_q);
@@ -275,8 +287,8 @@ end
 
 dot11 dot11_inst (
     .clock(clock),
-    .reset(reset),
     .enable(enable),
+    .reset(reset),
 
     //.set_stb(set_stb),
     //.set_addr(set_addr),
@@ -290,21 +302,38 @@ dot11 dot11_inst (
     .sample_in_strobe(sample_in_strobe),
     .soft_decoding(1'b1),
 
+    .pkt_header_valid_strobe(pkt_header_valid_strobe),
+    .pkt_len(pkt_len),
+    .pkt_len_total(pkt_len_total),
+    .byte_out_strobe(byte_out_strobe),
+    .byte_out(byte_out),
+    .byte_count_total(byte_count_total),
+    .byte_count(byte_count),
+    .fcs_out_strobe(fcs_out_strobe),
+    .fcs_ok(fcs_ok),
+
     .state(dot11_state),
 
     .power_trigger(power_trigger),
+
     .short_preamble_detected(short_preamble_detected),
 
     .sync_long_metric(sync_long_metric),
     .sync_long_metric_stb(sync_long_metric_stb),
     .long_preamble_detected(long_preamble_detected),
-
     .sync_long_out(sync_long_out),
     .sync_long_out_strobe(sync_long_out_strobe),
 
     .equalizer_out(equalizer_out),
     .equalizer_out_strobe(equalizer_out_strobe),
 
+    .legacy_sig_stb(legacy_sig_stb),
+    .legacy_rate(legacy_rate),
+    .legacy_sig_rsvd(legacy_sig_rsvd),
+    .legacy_len(legacy_len),
+    .legacy_sig_parity(legacy_sig_parity),
+    .legacy_sig_tail(legacy_sig_tail),
+
     .demod_out(demod_out),
     .demod_out_strobe(demod_out_strobe),
 
@@ -315,24 +344,7 @@ dot11 dot11_inst (
     .conv_decoder_out_stb(conv_decoder_out_stb),
 
     .descramble_out(descramble_out),
-    .descramble_out_strobe(descramble_out_strobe),
+    .descramble_out_strobe(descramble_out_strobe)
-
-    .pkt_header_valid_strobe(pkt_header_valid_strobe),
-    .byte_out(byte_out),
-    .byte_out_strobe(byte_out_strobe),
-    .fcs_out_strobe(fcs_out_strobe),
-    .fcs_ok(fcs_ok),
-    .byte_count_total(byte_count_total),
-    .byte_count(byte_count),
-    .pkt_len_total(pkt_len_total),
-    .pkt_len(pkt_len),
-
-    .legacy_rate(legacy_rate),
-    .legacy_sig_rsvd(legacy_sig_rsvd),
-    .legacy_len(legacy_len),
-    .legacy_sig_parity(legacy_sig_parity),
-    .legacy_sig_tail(legacy_sig_tail),
-    .legacy_sig_stb(legacy_sig_stb)
 );
 
 /*

verilog/equalizer.v

@@ -9,6 +9,7 @@ module equalizer
     input [31:0] sample_in,
     input sample_in_strobe,
     input ht_next,
+    input pkt_ht,
 
     output [31:0] phase_in_i,
     output [31:0] phase_in_q,
@@ -22,7 +23,11 @@ module equalizer
     output reg [31:0] sample_out,
     output reg sample_out_strobe,
     
-    output reg [2:0] state
+    output reg [2:0] state,
+
+    // for side channel
+    output wire [31:0] csi,
+    output wire csi_valid
 );
 
 
@@ -168,12 +173,16 @@ wire lts_div_out_stb = div_out_stb;
 reg prod_in_strobe;
 wire prod_out_strobe;
 
+// for side channel
+reg sample_in_strobe_dly;
+assign csi = {lts_i_out, lts_q_out};
+assign csi_valid = ( (num_ofdm_sym == 1 || (pkt_ht==1 && num_ofdm_sym==5)) && state == S_CALC_FREQ_OFFSET && sample_in_strobe_dly == 1 && enable && (~reset) );
+
 /*
 // =============save signal to file for matlab bit-true comparison===========
 integer file_open_trigger = 0;
 integer new_lts_fd, phase_offset_pilot_input_fd, phase_offset_lts_input_fd, phase_offset_pilot_fd, phase_offset_pilot_sum_fd, phase_offset_phase_out_fd, rot_out_fd, equalizer_prod_fd, equalizer_prod_scaled_fd, equalizer_mag_sq_fd, equalizer_out_fd;
 
-reg sample_in_strobe_dly;
 wire signed [15:0] norm_i_signed, norm_q_signed;
 assign norm_i_signed = sample_out[31:16];
 assign norm_q_signed = sample_out[15:0];
@@ -201,7 +210,6 @@ always @(posedge clock) begin
         equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
     end
 
-    sample_in_strobe_dly <= sample_in_strobe;
     if (num_ofdm_sym == 1 && state == S_CALC_FREQ_OFFSET && sample_in_strobe_dly == 1 && enable && (~reset) ) begin
         $fwrite(new_lts_fd, "%d %d\n", lts_i_out, lts_q_out);
         $fflush(new_lts_fd);
@@ -455,6 +463,7 @@ always @(posedge clock) begin
 
         state <= S_FIRST_LTS;
     end else if (enable) begin
+        sample_in_strobe_dly <= sample_in_strobe;
         case(state)
             S_FIRST_LTS: begin
                 // store first LTS as is

verilog/openofdm_rx.v

@@ -30,6 +30,13 @@
 		output wire [15:0] byte_count,
 		output wire fcs_out_strobe,
 		output wire fcs_ok,
+		// for side channel
+    	output wire [31:0] csi,
+    	output wire csi_valid,
+		output wire signed [31:0] phase_offset_taken,
+		output wire [31:0] equalizer,
+		output wire equalizer_valid,
+		output wire ofdm_symbol_eq_out_pulse,
 
 		// axi lite based register configuration interface
 		input  wire s00_axi_aclk,
@@ -92,21 +99,6 @@
     wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg31; 
 	*/
 
-	wire [3:0] state;
-	wire state_changed;
-	reg [31:0] state_history;
-
-	assign slv_reg20 = state_history;
-
-	always @(posedge s00_axi_aclk) begin
-		if (s00_axi_aresetn==0) begin
-			state_history <= 0;
-		end else if (state_changed) begin
-			state_history[3:0] <= state;
-			state_history[31:4] <= state_history[27:0];
-		end 
-	end
-
 	dot11 # ( 
 	) dot11_i (
 		.clock(s00_axi_aclk),
@@ -147,7 +139,7 @@
 		.state(state),
 		.status_code(),
 		.state_changed(state_changed),
-
+		.state_history(slv_reg20),
 		// power trigger
 		.power_trigger(),
 
@@ -161,12 +153,14 @@
 		.long_preamble_detected(),
 		.sync_long_out(),
 		.sync_long_out_strobe(),
+		.phase_offset_taken(phase_offset_taken),
 		.sync_long_state(),
 
 		// equalizer
-		.equalizer_out(),
+		.equalizer_out(equalizer),
-		.equalizer_out_strobe(),
+		.equalizer_out_strobe(equalizer_valid),
-		.equalizer_state(),
+		.equalizer_state(equalizer_state),
+		.ofdm_symbol_eq_out_pulse(ofdm_symbol_eq_out_pulse),
 
 		// legacy signal info
 		.legacy_sig_stb(),
@@ -202,7 +196,11 @@
 		.conv_decoder_out_stb(),
 
 		.descramble_out(),
-		.descramble_out_strobe()
+		.descramble_out_strobe(),
+
+		// for side channel
+		.csi(csi),
+		.csi_valid(csi_valid)
 	);
 
 	openofdm_rx_s_axi # ( 

verilog/sync_long.v

@@ -19,6 +19,7 @@ module sync_long (
     output reg sample_out_strobe,
     output reg [15:0] num_ofdm_symbol,
 
+    output reg signed [31:0] phase_offset_taken,
     output reg [2:0] state
 );
 `include "common_params.v"
@@ -359,6 +360,7 @@ always @(posedge clock) begin
                         num_ofdm_symbol <= 0;
                         phase_correction <= 0;
                         next_phase_correction <= phase_offset;
+                        phase_offset_taken <= phase_offset;
                         state <= S_FFT;
                     end else begin
                         state <= S_IDLE;