Sebastian Sumpf fd0e6685fc riscv: Use Qemu and update to ISA v1.10 ... - remove Spike/BBL support in favour of Qemu (>=4.2.1) - add 'riscv_qemu' board, remove 'spike' board' - update to privileged ISA v1.10 (from v1.9.1) - use direct system calls for privileged core threads (they call into the kernel and don't use mode changing system calls, i.e. 'ecall', semantics) - use 'OpenSBI' semtantics for SBI calls (to machine mode) instead of BBL issue #4012		2021-02-23 12:02:44 +01:00
..
bootstrap	riscv: Use Qemu and update to ISA v1.10	2021-02-23 12:02:44 +01:00
core	riscv: Use Qemu and update to ISA v1.10	2021-02-23 12:02:44 +01:00
include	riscv: Use Qemu and update to ISA v1.10	2021-02-23 12:02:44 +01:00
lib	base-hw: coding style	2021-02-23 12:02:41 +01:00
test	base-hw: coding style	2021-02-23 12:02:41 +01:00
timer/hw	timeout: rework timeout framework	2020-10-09 13:35:56 +02:00