Commit Graph

491 Commits

Author SHA1 Message Date
Norman Feske
99e7f26b99 Remove base/include/base/errno.h, fix 2015-03-19 08:57:20 +01:00
Norman Feske
e8336acafc base,os: Coding-style unification
Fixes 
2015-03-13 12:17:23 +01:00
Norman Feske
56ed7addbc base: fix misleading ROM-connection error message 2015-03-04 17:32:20 +01:00
Martin Stein
c78efd4428 odroid_xu: prevent tests with sd/platform/ahci/fb
Drivers like SD-Card, platform, AHCI, and framebuffer are specified as Exynos5
compliant. But they are at least not compliant with Odroid-XU although this is
Exynos5. Thus, prevent tests that rely on such drivers when building for
hw_odoid_xu. Furthermore, make previous Arndale regulator/consts.h,
uart_defs.h, and some Board_base enums available to all Exynos5 builds to
enable at least building the drivers.

Fixes 
2015-02-27 11:48:36 +01:00
Martin Stein
be392b3bf9 hw: support USB-Armory board
The USB Armory is almost the same as the i.MX53-QSB but it uses only
one of the two RAM banks available in i.MX53. Furthermore we use the USB
Armory only with Trustzone enabled.

Ref 
2015-02-27 11:48:35 +01:00
Stefan Kalkowski
7582396e9c hw_arndale: enable ARM virtualization extensions
* enables world-switch using ARM virtualization extensions
* split TrustZone and virtualization extensions hardly from platforms,
  where it is not used
* extend 'Vm_session' interface to enable configuration of guest-physical memory
* introduce VM destruction syscall
* add virtual machine monitor for hw_arndale that emulates a simplified version
  of ARM's Versatile Express Cortex A15 board for a Linux guest OS

Fixes 
2015-02-27 11:48:05 +01:00
Stefan Kalkowski
e7dad39016 uart_drv: enable RX channel for exynos5 driver
This is useful for automated tests on this platform, where the run script
wants to interact with some component via terminal

Ref 
2015-02-27 11:48:05 +01:00
Stefan Kalkowski
a40932a324 hw: refactor irq controllers
* name irq controller memory mapped I/O regions consistently
  in board descriptions
* move irq controller and timer memory mapped I/O region descriptions
  from cpu class to board class
* eliminate artificial distinction between flavors of ARM's GIC
* factor cpu local initialization out of ARM's GIC interface description,
  which is needed if the GIC is initialized differently e.g. for TrustZone

Ref 
2015-02-27 11:43:56 +01:00
Alexander Boettcher
a594ae703d base: fix location_of_index affinity calculation
Take care that ypos parameter is smaller than height().
If it is not - wrap around.

Issue .
2015-02-27 11:43:55 +01:00
Alexander Boettcher
8c66a4b1be base: support phys range specifier in ram_session
Fixes 
2015-02-16 13:40:38 +01:00
Alexander Boettcher
95ff5ba11d base: support range restriction in allocator
Issue 
2015-02-16 13:40:38 +01:00
Stefan Kalkowski
a3abf74d1e hw: remove code duplication related to Exynos5 SoC
Fixes 
2015-02-16 13:40:36 +01:00
Norman Feske
671682cb6a base: use reinterpret_cast for symbol lookup
This patch changes the Shared_object::lookup function to use a
reinterpret_cast instead of a static_cast to allow the conversion
from symbol addresses to arbitrary pointers.
2015-01-26 12:28:42 +01:00
Stefan Kalkowski
901bff813d imx31: remove platform completely (fix ) 2015-01-12 14:24:15 +01:00
Martin Stein
9a4a0448be hw vea9x4: remove trustzone support
When building Genode for VEA9X4 as micro-hypervisor protected by the ARM
TrustZone hardware we ran into limitations regarding our basic daily
testing routines. The most significant is that, when speaking about RAM
partitioning, the only available options are to configure the whole SRAM
to be secure and the whole DDR-RAM to be non-secure or vice versa. The
SRAM however provides only 32 MB which isn't enough for both a
representative non-secure guest OS or a secure Genode that is still
capable of passing our basic tests. This initiated our decision to
remove the VEA9X4 TrustZone-support.

Fixes 
2015-01-08 13:28:42 +01:00
Martin Stein
e63092f1dd hw & cortex_a9: fix scheduling-timer speed
The estimation of the input clock of the Cortex A9 Private Timer module
was pretty miserable at every Cortex A9 board.

Fixes 
2015-01-06 15:22:07 +01:00
Christian Helmuth
f9422b241f Fix compiler warning about uninitialized variable
Fixes 
2014-12-01 17:29:17 +01:00
Stefan Kalkowski
4d3fa001e0 hw: remove memory region duplicate (fix )
On the Versatile Express Cortex A9x4 platform the first memory region
0x0 - 0x4000000 is a hardware remapped memory area, containing flash
and DDR RAM copies and thus should not be added in addition to all
DDR RAM regions and the SRAM region.
2014-11-28 12:02:40 +01:00
Martin Stein
8f9355b360 thread API & CPU session: accounting of CPU quota
In the init configuration one can configure the donation of CPU time via
'resource' tags that have the attribute 'name' set to "CPU" and the
attribute 'quantum' set to the percentage of CPU quota that init shall
donate. The pattern is the same as when donating RAM quota.

! <start name="test">
!   <resource name="CPU" quantum="75"/>
! </start>

This would cause init to try donating 75% of its CPU quota to the child
"test".  Init and core do not preserve CPU quota for their own
requirements by default as it is done with RAM quota.

The CPU quota that a process owns can be applied through the thread
constructor. The constructor has been enhanced by an argument that
indicates the percentage of the programs CPU quota that shall be granted
to the new thread. So 'Thread(33, "test")' would cause the backing CPU
session to try to grant 33% of the programs CPU quota to the thread
"test". By now, the CPU quota of a thread can't be altered after
construction. Constructing a thread with CPU quota 0 doesn't mean the
thread gets never scheduled but that the thread has no guaranty to receive
CPU time. Such threads have to live with excess CPU time.

Threads that already existed in the official repositories of Genode were
adapted in the way that they receive a quota of 0.

This commit also provides a run test 'cpu_quota' in base-hw (the only
kernel that applies the CPU-quota scheme currently). The test basically
runs three threads with different physical CPU quota. The threads simply
count for 30 seconds each and the test then checks wether the counter
values relate to the CPU-quota distribution.

fix 
2014-11-28 12:02:37 +01:00
Martin Stein
ec6c19a487 base: memory barriers in lock implementations
The memory barrier prevents the compiler from changing the program order
of memory accesses in such a way that accesses to the guarded resource
get outside the guarded stage. As cmpxchg() defines the start of the
guarded stage it also represents an effective memory barrier.

On x86, the architecture ensures to not reorder writes with older reads,
writes to memory with other writes (except in cases that are not
relevant for our locks), or read/write instructions with I/O
instructions, locked instructions, and serializing instructions.

However on ARM, the architectural memory model allows not only that
memory accesses take local effect in another order as their program
order but also that different observers (components that can access
memory like data-busses, TLBs and branch predictors) observe these
effects each in another order. Thus, a correct program order isn't
sufficient for a correct observation order. An additional architectural
preservation of the memory barrier is needed to achieve this.

Fixes 
2014-11-28 12:02:34 +01:00
Martin Stein
8dad54c914 hw: fix scheduler timing on prio preemption
Previously, the timer was used to remember the state of the time slices.
This was sufficient before priorities entered the scene as a thread always
received a fresh time slice when he was scheduled away. However, with
priorities this isn't always the case. A thread can be preempted by another
thread due to a higher priority. In this case the low-priority thread must
remember how much time he has consumed from its current time slice because
the timer gets re-programmed. Otherwise, if we have high-priority threads
that block and unblock with high frequency, the head of the next lower
priority would start with a fresh time slice all the time and is never
superseded.

fix 
2014-11-14 12:00:45 +01:00
Christian Helmuth
2eca4ec98b base: document specifics of Slab::alloc()
Also removed unimplemented overload of alloc() with no parameters.
2014-11-12 14:44:16 +01:00
Sebastian Sumpf
5a821d4c92 base: Genode's dynamic linker
Issue 
2014-11-12 14:44:15 +01:00
Norman Feske
a7fa0ccd06 base: add 'String::operator!=' 2014-10-13 15:21:53 +02:00
Norman Feske
58a1e42201 hw/rpi: USB SOF interrupt filtering 2014-10-13 14:52:43 +02:00
Christian Prochaska
4539eb7512 heap: release some memory to the RAM session
With this patch, allocations >= 64K are fulfilled by dedicated
dataspaces, which are released to the RAM session when not needed
anymore.

Fixes 
2014-10-10 13:02:38 +02:00
Christian Helmuth
0b5f901e58 Log name of exiting child from Child::exit()
Fixes .
2014-09-11 10:23:39 +02:00
Martin Stein
a5cf09fa6e hw: re-organize file structure
fix 
2014-08-15 10:19:48 +02:00
Norman Feske
0be6817226 Add 'Weak_ptr' to the public Genode API
So far, the lifetime-management utilities 'Weak_ptr' and 'Locked_ptr'
had been preserved for core-internal use only. However, the utilities
are handy for many use cases outside of core where object lifetimes
must be managed. So we promote them to the public API.
2014-08-11 15:55:32 +02:00
Norman Feske
c652655bcb Add Rom_session::update
The new Rom_session::update function can be used to request the update of
an existing ROM dataspace. If the new data fits into the existing
dataspace, a subsequent call of 'dataspace' can be omitted. This way,
ROM dataspace updates don't suffer from page-fault-handling costs that
would occur when replacing the dataspace with each update.
2014-08-11 15:55:31 +02:00
Christian Prochaska
a46de84f89 Fix race condition in page fault notification
When a page fault cannot be resolved, the GDB monitor can get a hint about
which thread faulted by evaluating the thread state object returned by
'Cpu_session::state()'. Unfortunately, with the current implementation,
the signal which informs GDB monitor about the page fault is sent before
the thread state object of the faulted thread has been updated, so it
can happen that the faulted thread cannot be determined immediately
after receiving the signal.

With this commit, the thread state gets updated before the signal is sent.

At least on base-nova it can also happen that the thread state is not
accessible yet after receiving the page fault notification. For this
reason, GDB monitor needs to retry its query until the state is
accessible.

Fixes .
2014-07-24 10:18:07 +02:00
Stefan Kalkowski
1c11099f09 hw: clean cache lines of altered translation table
For Cortex A8, and ARM1176JZF clean cache lines of altered MMU translation
tables.

Fix 
2014-07-09 16:26:06 +02:00
Christian Helmuth
f7a7421091 Configurable clearing of array in Bit_array_base
Fixes .
2014-07-09 16:26:04 +02:00
Stefan Kalkowski
42397cb512 os: avoid deadlock in packet stream (fix )
Respectively resend a packet-stream-not-empty signal when a new signal handler
gets registered.
2014-06-26 12:14:03 +02:00
Stefan Kalkowski
7b5237f9ff hw: add CSU I/O memory to core's memory regions
The central security regions has to be mapped when starting the hw-kernel
on the i.MX53 and using the TrustZone mechanisms.

Ref 
2014-06-26 10:57:27 +02:00
Stefan Kalkowski
786fe805da base: introduce caching attributes (fix )
On ARM it's relevant to not only distinguish between ordinary cached memory
and write-combined one, but also having non-cached memory too. To insert the
appropriated page table entries e.g.: in the base-hw kernel, we need to preserve
the information about the kind of memory from allocation until the pager
resolves a page fault. Therefore, this commit introduces a new Cache_attribute
type, and replaces the write_combined boolean with the new type where necessary.
2014-06-26 10:57:26 +02:00
Christian Helmuth
7abc1733c5 util: abort construction of zero-sized bit arrays 2014-06-26 10:57:25 +02:00
Stefan Kalkowski
05603951b6 hw: enable and maintain outer l2 cache
Fix 
2014-06-26 10:57:25 +02:00
Norman Feske
6125e10be6 base: Never copy the dealloc argument for destroy
By using &&, we prevent the accidental copying of deallocator instances,
passed to the destroy function. We always want to take the deallocator
as reference or pointer.
2014-06-26 10:57:25 +02:00
Christian Prochaska
078883fda3 base: interface for D- and I-cache synchronization
On ARM, when machine instructions get written into the data cache
(for example by a JIT compiler), one needs to make sure that the
instructions get written out to memory and read from memory into
the instruction cache before they get executed. This functionality
is usually provided by a kernel syscall and this patch adds a generic
interface for Genode applications to use it.

Fixes .
2014-05-27 11:14:45 +02:00
Norman Feske
ca971bbfd8 Move repositories to 'repos/' subdirectory
This patch changes the top-level directory layout as a preparatory
step for improving the tools for managing 3rd-party source codes.
The rationale is described in the issue referenced below.

Issue 
2014-05-14 16:08:00 +02:00