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https://github.com/genodelabs/genode.git
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uart_drv: enable RX channel for exynos5 driver
This is useful for automated tests on this platform, where the run script wants to interact with some component via terminal Ref #1405
This commit is contained in:
Stefan Kalkowski
Christian Helmuth
parent
1e3c80ff5b
commit
e7dad39016
@ -24,145 +24,181 @@ namespace Genode
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*/
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class Exynos_uart_base : Mmio
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{
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/**
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* Line control
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*/
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struct Ulcon : Register<0x0, 32>
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{
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struct Word_length : Bitfield<0, 2> { enum { _8_BIT = 3 }; };
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struct Stop_bits : Bitfield<2, 1> { enum { _1_BIT = 0 }; };
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struct Parity_mode : Bitfield<3, 3> { enum { NONE = 0 }; };
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struct Infrared_mode : Bitfield<6, 1> { };
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protected:
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/**
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* Initialization value
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* Line control
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*/
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static access_t init_value()
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struct Ulcon : Register<0x0, 32>
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{
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return Word_length::bits(Word_length::_8_BIT) |
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Stop_bits::bits(Stop_bits::_1_BIT) |
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Parity_mode::bits(Parity_mode::NONE) |
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Infrared_mode::bits(0);
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}
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};
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struct Word_length : Bitfield<0, 2> { enum { _8_BIT = 3 }; };
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struct Stop_bits : Bitfield<2, 1> { enum { _1_BIT = 0 }; };
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struct Parity_mode : Bitfield<3, 3> { enum { NONE = 0 }; };
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struct Infrared_mode : Bitfield<6, 1> { };
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/**
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* Control
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*/
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struct Ucon : Register<0x4, 32>
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{
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struct Receive_mode : Bitfield<0, 2> { enum { IRQ_POLL = 1 }; };
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struct Transmit_mode : Bitfield<2, 2> { enum { IRQ_POLL = 1 }; };
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struct Send_brk_signal : Bitfield<4, 1> { };
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struct Loop_back_mode : Bitfield<5, 1> { };
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struct Rx_err_irq : Bitfield<6, 1> { };
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struct Rx_timeout : Bitfield<7, 1> { };
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struct Rx_irq_type : Bitfield<8, 1> { enum { LEVEL = 1 }; };
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struct Tx_irq_type : Bitfield<9, 1> { enum { LEVEL = 1 }; };
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struct Rx_to_dma_susp : Bitfield<10, 1> { };
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struct Rx_to_empty_rx : Bitfield<11, 1> { };
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struct Rx_to_interval : Bitfield<12, 4> { };
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struct Rx_dma_bst_size : Bitfield<16, 3> { };
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struct Tx_dma_bst_size : Bitfield<20, 3> { };
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/**
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* Initialization value
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*/
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static access_t init_value()
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{
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return Word_length::bits(Word_length::_8_BIT) |
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Stop_bits::bits(Stop_bits::_1_BIT) |
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Parity_mode::bits(Parity_mode::NONE) |
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Infrared_mode::bits(0);
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}
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};
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/**
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* Initialization value
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* Control
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*/
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static access_t init_value()
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struct Ucon : Register<0x4, 32>
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{
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return Receive_mode::bits(Receive_mode::IRQ_POLL) |
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Transmit_mode::bits(Transmit_mode::IRQ_POLL) |
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Send_brk_signal::bits(0) |
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Loop_back_mode::bits(0) |
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Rx_err_irq::bits(1) |
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Rx_timeout::bits(0) |
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Rx_irq_type::bits(Rx_irq_type::LEVEL) |
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Tx_irq_type::bits(Tx_irq_type::LEVEL) |
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Rx_to_dma_susp::bits(0) |
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Rx_to_empty_rx::bits(0) |
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Rx_to_interval::bits(3) |
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Rx_dma_bst_size::bits(0) |
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Tx_dma_bst_size::bits(0);
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}
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};
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struct Receive_mode : Bitfield<0, 2> { enum { IRQ_POLL = 1 }; };
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struct Transmit_mode : Bitfield<2, 2> { enum { IRQ_POLL = 1 }; };
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struct Send_brk_signal : Bitfield<4, 1> { };
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struct Loop_back_mode : Bitfield<5, 1> { };
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struct Rx_err_irq : Bitfield<6, 1> { };
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struct Rx_timeout : Bitfield<7, 1> { };
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struct Rx_irq_type : Bitfield<8, 1> { enum { LEVEL = 1 }; };
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struct Tx_irq_type : Bitfield<9, 1> { enum { LEVEL = 1 }; };
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struct Rx_to_dma_susp : Bitfield<10, 1> { };
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struct Rx_to_empty_rx : Bitfield<11, 1> { };
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struct Rx_to_interval : Bitfield<12, 4> { };
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struct Rx_dma_bst_size : Bitfield<16, 3> { };
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struct Tx_dma_bst_size : Bitfield<20, 3> { };
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/**
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* FIFO control
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*/
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struct Ufcon : Register<0x8, 32>
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{
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struct Fifo_en : Bitfield<0, 1> { };
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struct Rx_fifo_rst : Bitfield<1, 1> { };
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struct Tx_fifo_rst : Bitfield<2, 1> { };
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struct Rx_fifo_trigger : Bitfield<4, 3> { };
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struct Tx_fifo_trigger : Bitfield<8, 3> { };
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/**
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* Initialization value
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*/
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static access_t init_value()
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{
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return Receive_mode::bits(Receive_mode::IRQ_POLL) |
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Transmit_mode::bits(Transmit_mode::IRQ_POLL) |
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Rx_timeout::bits(1);
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}
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};
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/**
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* Initialization value
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* FIFO control
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*/
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static access_t init_value()
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struct Ufcon : Register<0x8, 32>
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{
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return Fifo_en::bits(1) |
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Rx_fifo_rst::bits(0) |
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Tx_fifo_rst::bits(0) |
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Rx_fifo_trigger::bits(0) |
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Tx_fifo_trigger::bits(0);
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}
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};
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/**
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* Modem control
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*/
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struct Umcon : Register<0xc, 32>
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{
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struct Send_request : Bitfield<0, 1> { };
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struct Modem_irq : Bitfield<3, 1> { };
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struct Auto_flow_ctl : Bitfield<4, 1> { };
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struct Rts_trigger : Bitfield<5, 3> { };
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struct Fifo_en : Bitfield<0, 1> { };
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struct Rx_fifo_rst : Bitfield<1, 1> { };
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struct Tx_fifo_rst : Bitfield<2, 1> { };
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};
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/**
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* Initialization value
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* Modem control
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*/
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static access_t init_value()
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struct Umcon : Register<0xc, 32>
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{
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return Send_request::bits(0) |
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Modem_irq::bits(0) |
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Auto_flow_ctl::bits(0) |
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Rts_trigger::bits(0);
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struct Send_request : Bitfield<0, 1> { };
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struct Modem_irq : Bitfield<3, 1> { };
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struct Auto_flow_ctl : Bitfield<4, 1> { };
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struct Rts_trigger : Bitfield<5, 3> { };
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/**
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* Initialization value
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*/
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static access_t init_value()
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{
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return Send_request::bits(0) |
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Modem_irq::bits(0) |
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Auto_flow_ctl::bits(0) |
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Rts_trigger::bits(0);
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}
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};
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/**
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* FIFO status
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*/
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struct Ufstat : Register<0x18, 32>
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{
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struct Rx_fifo_count : Bitfield<0, 8> { };
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struct Rx_fifo_full : Bitfield<8, 1> { };
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struct Tx_fifo_full : Bitfield<24, 1> { };
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};
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/**
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* Transmit buffer
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*/
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struct Utxh : Register<0x20, 32>
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{
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struct Transmit_data : Bitfield<0, 8> { };
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};
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/**
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* Receive buffer
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*/
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struct Urxh : Register<0x24, 32>
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{
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struct Receive_data : Bitfield<0, 8> { };
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};
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/**
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* Baud Rate Divisor
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*/
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struct Ubrdiv : Register<0x28, 32>
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{
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struct Baud_rate_div : Bitfield<0, 16> { };
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};
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/**
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* Fractional part of Baud Rate Divisor
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*/
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struct Ufracval : Register<0x2c, 32>
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{
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struct Baud_rate_frac : Bitfield<0, 4> { };
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};
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/**
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* Interrupt mask register
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*/
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template <unsigned OFF>
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struct Uintx : Register<OFF, 32>
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{
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struct Rxd : Register<OFF, 32>::template Bitfield<0, 1> { };
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struct Error : Register<OFF, 32>::template Bitfield<1, 1> { };
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struct Txd : Register<OFF, 32>::template Bitfield<2, 1> { };
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struct Modem : Register<OFF, 32>::template Bitfield<3, 1> { };
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};
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using Uintp = Uintx<0x30>;
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using Uintm = Uintx<0x38>;
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void _rx_enable()
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{
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write<Ufcon::Fifo_en>(1);
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/* mask all IRQs except receive IRQ */
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write<Uintm>(Uintm::Error::bits(1) |
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Uintm::Txd::bits(1) |
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Uintm::Modem::bits(1));
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/* clear pending IRQs */
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write<Uintp>(Uintp::Rxd::bits(1) |
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Uintp::Error::bits(1) |
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Uintp::Txd::bits(1) |
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Uintp::Modem::bits(1));
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}
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};
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/**
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* FIFO status
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*/
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struct Ufstat : Register<0x18, 32>
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{
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struct Tx_fifo_full : Bitfield<24, 1> { };
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};
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bool _rx_avail() {
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return (read<Ufstat>() & (Ufstat::Rx_fifo_count::bits(0xff)
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| Ufstat::Rx_fifo_full::bits(1))); }
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/**
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* Transmit buffer
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*/
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struct Utxh : Register<0x20, 32>
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{
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struct Transmit_data : Bitfield<0, 8> { };
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};
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/**
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* Return character received via UART
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*/
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char _rx_char()
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{
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read<Ufcon>();
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char c = read<Urxh::Receive_data>();
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/**
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* Baud Rate Divisor
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*/
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struct Ubrdiv : Register<0x28, 32>
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{
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struct Baud_rate_div : Bitfield<0, 16> { };
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};
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/**
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* Fractional part of Baud Rate Divisor
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*/
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struct Ufracval : Register<0x2c, 32>
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{
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struct Baud_rate_frac : Bitfield<0, 4> { };
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};
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/* clear pending RX IRQ */
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write<Uintp>(Uintp::Rxd::bits(1));
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return c;
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}
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public:
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@ -176,10 +212,14 @@ namespace Genode
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Exynos_uart_base(addr_t const base, unsigned const clock,
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unsigned const baud_rate) : Mmio(base)
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{
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/* RX and TX FIFO reset */
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write<Ufcon::Rx_fifo_rst>(1);
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write<Ufcon::Tx_fifo_rst>(1);
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while (read<Ufcon::Rx_fifo_rst>() || read<Ufcon::Tx_fifo_rst>()) ;
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/* init control registers */
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write<Ulcon>(Ulcon::init_value());
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write<Ucon>(Ucon::init_value());
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write<Ufcon>(Ufcon::init_value());
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write<Umcon>(Umcon::init_value());
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/* apply baud rate */
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@ -30,6 +30,11 @@ class Exynos_uart : public Genode::Exynos_uart_base,
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public Uart::Driver,
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public Genode::Irq_handler
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{
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private:
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Uart::Char_avail_callback &_char_avail_callback;
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Genode::Irq_activation _irq_activation;
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public:
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/**
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@ -37,24 +42,31 @@ class Exynos_uart : public Genode::Exynos_uart_base,
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*/
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Exynos_uart(Genode::Attached_io_mem_dataspace *uart_mmio, int irq_number,
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unsigned baud_rate, Uart::Char_avail_callback &callback)
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:
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Exynos_uart_base((Genode::addr_t)uart_mmio->local_addr<void>(),
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Genode::Board_base::UART_2_CLOCK, baud_rate) { }
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: Exynos_uart_base((Genode::addr_t)uart_mmio->local_addr<void>(),
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Genode::Board_base::UART_2_CLOCK, baud_rate),
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_char_avail_callback(callback),
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_irq_activation(irq_number, *this, sizeof(Genode::addr_t) * 1024) {
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_rx_enable(); }
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/**
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* * IRQ handler interface **
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*/
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void handle_irq(int irq_number) { }
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/**
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* * UART driver interface **
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*/
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/***************************
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** IRQ handler interface **
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***************************/
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void handle_irq(int irq_number)
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{
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/* inform client about the availability of data */
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_char_avail_callback();
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}
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/***************************
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** UART driver interface **
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***************************/
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void put_char(char c) { Exynos_uart_base::put_char(c); }
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bool char_avail() { return false; }
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char get_char() { return 0; }
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bool char_avail() { return _rx_avail(); }
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char get_char() { return _rx_char(); }
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void baud_rate(int bits_per_second) {}
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};
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