Commit Graph

1079 Commits

Author SHA1 Message Date
Martin Stein
f74962bdad base-hw scheduler: fix bug on removing head
The scheduler did not consider the consumed quota during a call to "update"
if the head that consumed the quota was removed from the scheduler. When this
occured, the internal round time did not advance as expected but remained at
its previous value untile the next call to "update" (without a removed head)
This commit introduces a new flag that is set only when the head gets removed
in order to detect and handle the situation correctly on the next call to
"update".

Ref #4151
Ref #4710
2023-01-24 12:07:31 +01:00
Martin Stein
ab298b6337 base-hw scheduler: fix ready method
Setting the _need_to_schedule member in the 'ready' method of the scheduler
was not done correctly. At least, the _need_to_schedule was set true in
situations were the head was not outdated by the 'ready' operation.

Ref #4151
2023-01-24 12:07:31 +01:00
Stefan Kalkowski
1151706243 hw: rename functions of Ipc_node class signature
* Remove *request* in context of: wait, reply, send to shorten it.
* Use ready_to_* instead of can_*, which is regularily used in Genode's APIs
* Replace helping_sink with helping_destination, as destination is more common

Ref genodelabs/genode#4704
2023-01-24 12:07:30 +01:00
Stefan Kalkowski
fd3c70ec5b hw: mark threads as dead in case of ipc violations
The IPC protcol violations are:

* Sending to an unknown thread (cap)
* Waiting for messages if a reply hasn't happened yet

This silents threads that otherwise repeatedly cause kernel messages
about the violation.

Ref genodelabs/genode#4704
2023-01-24 12:07:30 +01:00
Stefan Kalkowski
fc690f1c47 hw: re-work the ipc node's internal state machine
* Split the internal state into incoming and outgoing message relations
* Avoid fragmenting of one state like formerly '_state' and '_help'
* Remove pointer to caller, use incoming FIFO instead

This commit fixes at least two bugs that were triggered by tests that
destroy threads in many different states, like run/bomb:

* The '_help' data member was not reset reliable in each situation where a
  helping relationship came to an end. However, when we fixed this bug alone
  in the old state model, the issues remained. The new state model fixes
  this bug as well.

* A thread sometimes referenced an already dead thread as receiver. This caused
  the kernel IPC code to access the vtable of an object that didn't exist any
  longer. Note that the two threads were not in direct IPC relationship while
  the receiver was destroyed, so, there must have been an intermediate node
  between them. Due to the complexity of this problem, we eventually gave up
  pin-pointing the exact reason in the kernel IPC code. The issue disappeared
  with the new state model.

Fix genodelabs/genode#4704
2023-01-24 12:07:30 +01:00
Stefan Kalkowski
08c56e61e1 hw: avoid overhead for cache maintainance
When running on x86, and riscv never enter the kernel for cache maintainance,
but use the dummy implementation of the generic base library instead.

On ARMv8 it is not necessary to enter privileged mode for cache cleaning, and
unification of instruction/data cache, but only for invalidating cache lines
at all levels, which is necessary for the use cases, where this function it
needed (coherency of DMA memory).

Fix genodelabs/genode#4339
2023-01-24 12:07:29 +01:00
Josef Söntgen
66fd027b96 base-hw: introduce 'cache_line_size' call
This call is used to query the cache line size of the underlying CPU.
For now it is only implemented and used by 'arm_v8' platforms.

It does not distinguish between D-/I-cache sizes and always uses the
smallest size. Furthermore it does not account for any discrepancy
in 'big.little' CPUs.

Issue #4339.
2023-01-24 12:07:29 +01:00
Josef Söntgen
e8f748cfed base-hw: unprivileged cache maintenance on ARMv8
Set 'Sctlr_el1::Uci' bit to allow for executing cache clean and
invalidate instruction from user space.

Issue #4339.
2023-01-24 12:07:29 +01:00
Stefan Kalkowski
8fe7fa5532 hw: don't take the log backend's mutex in kernel
To prevent the kernel to deadlock, or call itself with a syscall when
using a lock potentially hold by a core thread, the log console's
backend for core (hw) gets replaced by a specific variant that checks
whether it runs in the kernel context before using the mutex.

Fix genodelabs/genode#3280
2023-01-24 12:07:29 +01:00
Christian Helmuth
8661936d7d base: aquire context mutex in local_submit()
Some signal-heavy scenarios (e.g., libc_integration) produced the
following warning that hinted a data race on signal data in the context
object.

  Warning: returning signal with num == 0

The cause was the use of Signal_context::local_submit() in the libc
introduced in

  424ed1b79a libc: remove Reconstructible / use local_submit in kernel

in combination with a missing context-mutex aquisition resulting in a
data race on Signal_context::_curr_signal.

Issue #3923
2023-01-24 12:07:27 +01:00
Christian Helmuth
b033b30f95 depot: update recipe hashes 2022-11-29 12:32:49 +01:00
Christian Prochaska
acb6bbb649 hw: fix 'Kernel::time()' deviation in RISC-V timer
Issue #4360
2022-11-29 12:29:57 +01:00
Christian Prochaska
345c01677d hw: fix 'Kernel::time()' deviation in ARM generic timer
Issue #4360
2022-11-29 12:29:57 +01:00
Christian Helmuth
c58d799f16 depot: update recipe hashes 2022-11-17 08:00:37 +01:00
Stefan Kalkowski
759ed40d98 hw: implement MSI support for x86
Fix genodelabs/genode#4633
2022-11-17 08:00:34 +01:00
Christian Helmuth
847266d027 depot: update recipe hashes 2022-10-12 14:31:50 +02:00
Martin Stein
665a551fcd base-hw & cortex_a9: consider timer IRQ unreliable
On some Cortex A9 platforms (Qemu 4.2.1 PBXA9), the IRQ status register is not
reliable. Sometimes, it indicates an IRQ too early, i.e., shortly before the
counter wraps. Therefore we have to accomplish wrap detection via counter
comparison only. We check whether the current counter value is higher than the
start counter value of the current timeout.

However, this implies that we have to take care to always read out the counter
before it hits the max timout value again. And, therefore, the max timeout
value has to be far away from the first value the counter has after wrapping.
Consequently, we propagate a max timeout value of half the max counter value.

Fixes #4209
2022-10-12 12:09:34 +02:00
Stefan Kalkowski
b85b3abe20 base-hw: update cpu_scheduler unit test
* Modernize routines, eliminate pointers, use constructibles, etc.
* Use absolute time instead of relative time consumption when
  updating the scheduler

Ref genodelabs/genode#4151
2022-10-12 11:59:08 +02:00
Stefan Kalkowski
debd41081e base-hw: optimize & cleanup scheduler
* Remove useless `ready_check` function
* Implement fine-grained checking when schedule updating is necessary

Ref genodelabs/genode#4151
2022-10-12 11:59:08 +02:00
Martin Stein
c23b74e150 base-hw: problems with timeout lib in src recipe
This commit fixes two issues with the timeout lib and the base-hw src recipe:

* Add source files of timeout lib to recipe content.
  The files weren't copied to the depot until now. However, the archive
  nonetheless built successfully because of the second issue that is described
  below.

* Get rid of the usage of the BASE_DIR variable in the timeout lib.
  The BASE_DIR variable always resolves to the repos/base directory even when
  building in a depot. That said, the use of BASE_DIR in make-files that are
  not part of the build system itself must be avoided. Instead, REP_DIR,
  REP_INC_DIR, and $(call select_from_repositories, ...) should be used.

Ref #4209
2022-10-12 11:59:08 +02:00
Stefan Kalkowski
0231ee4ad3 hw: don't halt kernel due to unknown cpu exception
Fix genodelabs/genode#4617
2022-10-12 11:59:08 +02:00
Christian Helmuth
3f1870841c depot: update recipe hashes 2022-09-21 12:19:10 +02:00
Norman Feske
7c3b9c843f base-hw: tighten src-archive content of lib/mk/
This patch refines the rules for generating a base-hw src archive
for a given board by enumerating the content of the lib/mk/spec/*
directories instead of including entire directories. This avoids
the inclusion of lib.mk files found in SoC-specific repositories
(like genode-allwinner) in the kernel source archives.

When building a binary archive from such a src archive with the changes
of issue #4599, the build system would otherwise try (and fail) to build
the libraries for the accidentally included lib.mk files.
2022-09-19 14:00:33 +02:00
Norman Feske
dd9e12601e Remove pseudo targets for building shared libs
Thanks to the change "build: support library builds via lib/<libname>",
shared libraries can now be built directly by the build system.

Issue #4599
2022-09-19 14:00:32 +02:00
Christian Helmuth
4dddc41b71 depot: update recipe hashes 2022-08-31 09:32:09 +02:00
Christian Helmuth
44e2cd14a0 depot: update recipe hashes 2022-08-17 12:03:26 +02:00
Sebastian Sumpf
b5c780993c board: Rename virt_qemu to virt_qemu_<arch>
Instead of having a generic "virt_qemu" board use "virt_qemu_<arch>" in
order to have a clean distinction between boards. Current supported
boards are "virt_qemu_arm_v7a", "virt_qemu_arm_v8a", and
"virt_qemu_riscv".

issue #4034
2022-08-17 12:03:26 +02:00
Stefan Kalkowski
f4f2b456b6 base-hw: invalidate VM TLB entries in deletion
This commit introduces a hypervisor calling interface. The host kernel can
use it to either switch to a guest VM, or to invalidate the TLB with
regard to a specified VM id.
The VM-specific TLB invalidation is called whenever a VM (Vcpu)
gets destroyed.

Fix genodelabs/genode#4528
2022-08-10 13:32:57 +02:00
Stefan Kalkowski
4382d29422 base-hw: invalidate TLB only once on ARMv8
Fix genodelabs/genode#4529
2022-08-10 13:32:57 +02:00
Stefan Kalkowski
d6592ca2cb base-hw: unset deleted PD values in MMU
When a PD gets deleted check whether it is active on the current CPU resp. MMU.
If yes, switch to core/kernel's PD to prevent that invalid page-tables or
address-space IDs are still in use. Moreover, whenever we switch to an idle
thread, we switch to kernel/core's PD too. Thereby, we prevent that vanished
PDs are still active on CPUs different from the one, where the core entrypoint
is active, which does the PD deletion.
This whole scheme is only valid under the assumption that core has only one
entrypoint running on one CPU.

Fix genodelabs/genode#4527
2022-08-10 13:32:57 +02:00
Stefan Kalkowski
5cfb9e3e9d base-hw: distinguish core, idle, user threads
Do not only distinguish core and user threads, but the idle threads too.
Instead of a boolean value, introduce a new thread type.

Ref genodelabs/genode#4527
2022-08-10 13:32:57 +02:00
Christian Helmuth
3105fa9e0f depot: update recipe hashes 2022-05-25 12:23:04 +02:00
Christian Helmuth
8ece236635 depot: update recipe hashes 2022-04-13 11:54:46 +02:00
Johannes Schlatow
d372afd81e base-hw: add bitfield to pl310
Enabling double linefills improves memcpy throughput.

genodelabs/genode#4456
2022-04-13 08:08:01 +02:00
Norman Feske
f3984ba5a9 base: declare build artifact for core
This is a generalization of the recent commit "base-hw: declare build
artifact for core".
2022-04-13 08:07:58 +02:00
Christian Helmuth
2b3370c8d8 depot: update recipe hashes 2022-02-28 11:46:35 +01:00
Stefan Kalkowski
b5b958c276 hw: unify architectural kernel interface header
Fix genodelabs/genode#4345
2022-02-28 11:45:18 +01:00
Piotr Tworek
e595b0b782 base-hw: Make sure MMU is initially disabled on ARMv8.
Genode code already expects MMU to be disabled when starting the
kernel. It is enabled eventually in Bootstrap::Platform::enable_mmu,
after setting up translation tables. Unfortunately nothing ensures
this is actually the case. If MMU happens to be enabled when entering
the kernel things go downhill pretty fast after we start messing with
TTBR.

This patch ensures MMU is disabled for EL1, EL2, EL3 dependent on the
exception level of the CPU core, which is entering the kernel.

This should allow base-hw to start correctly on Quartz64 A board.
2022-02-21 15:47:51 +01:00
Stefan Kalkowski
0c67d0838a hw: restrict page-table lookup to rw-pages
The `lookup_translation` function got introduced and is used only in the
context to proof whether a cache maintainance function can be executed
safely by the kernel. Unfortunately, it did not checked write permissions,
which can lead to permission faults. This commit restricts the lookup
function to only succeed when the target page is writeable. Consequently,
the lookup function gets renamed to `lookup_rw_translation`.

Fix genodelabs/genode#4348
2022-02-21 15:47:51 +01:00
Piotr Tworek
bade0a85e7 base-hw: Implement CPU core identification for Cortex-A55.
According to ARM Cortex-A55 Core Technical Reference Manual r1p0 the
lowest 8 bits (Aff0) of MPIDR register represent thread IDs within a
multi-threaded core. The actual core identification bits are in Aff1.
This layout can be identified by checking the MT bit of MPIDR register.
Basically, if MT=1 core id is in Aff1, if MT=0 core id is in Aff0.

Without this change Genode will identify all CPU cores on A55 as primary
(0) core.

Its worth to mention that Cortex-A55 by itself is not a multi-threaded
CPU. Aff0 values are always expected to be 0 for pure A55 cores. A55
cores can however be paired with cores that are multi-threaded. To
support such big.LITTLE CPUs in Genode we'd probably need to add a
different mechanism for mapping MPIDR values to logical, contignous
core IDs which Genode expects.

Ref:
https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch64-system-registers/mpidr-el1--multiprocessor-affinity-register--el1?lang=en
2022-02-15 15:27:29 +01:00
Norman Feske
649647538b depot: update recipe hashes 2022-02-15 10:23:59 +01:00
Piotr Tworek
5e93a5806b base-hw: Use softfp ABI on virt_qemu ARMv7.
The soft ABI implies purely software floating point implementation.
This is not the case for Genode however. For example core's
exception_vector.S uses vmsr instruction. This builds fine with with
GCC based toolchain, but clang with integrated-as complains:

src/core/spec/arm/exception_vector.S:122:2: error: instruction requires: VFP2
 vmsr fpexc, r1
 ^

Fix this by passing softfp to mfloat-abi command on ARMv7. This allows
usage of FP HW, but implies soft-floating point ABI.

Issue #4421
2022-02-15 10:23:58 +01:00
Piotr Tworek
4ae78639f5 base-hw: Fix invalid structure alignments.
According to C++11 reference:

  "If the strictest (largest) alignas on a declaration is weaker than
   the alignment it would have without any alignas specifiers (that is,
   weaker than its natural alignment or weaker than alignas on another
   declaration of the same object or type), the program is ill-formed:"

https://en.cppreference.com/w/cpp/language/alignas

The code requests 4 byte alignment for Genode::Arm_cpu::Context.
The Context structure inherits Genode::Arm_cpu::Fpu_context which
has minimum alignment requirement of 8 bytes, due to uint64_t d0_d31
member. This makes the 4 byte value in Context's alignas specifier
invalid (smaller than allowed minimum).

Similar situation takes place in Arm_64 case. The claimed minimum
alignment of Context is 8 bytes, but the fpu_state member imposes 16
bytes alignment (explicitly specified in Fpu_state declaration).

In both cases the code builds fine with GCC 8.3.0, but fails with
clang which claims that "requested alignment is less than minimum
alignment of X for type", where X is 8 on ARM and 16 on AArch64.

Ref: https://eel.is/c++draft/dcl.align#5

Issue #4421
2022-02-15 10:23:58 +01:00
Norman Feske
33b038e8a7 Consistent spelling of "writeable"
Fixes #4425
2022-02-15 10:23:58 +01:00
Norman Feske
50c2b0066f Remove 'Env::reinit' and 'Env::reinit_main_thread'
Fixes #4404
2022-02-15 10:17:28 +01:00
Norman Feske
ab0cba8ead base-hw: improve comments in kernel/interface.h 2022-02-15 10:10:02 +01:00
Norman Feske
90c446e565 base-hw: remove throw from ipc_reply_wait
Even though the use of the C++ exception mechanism (and the implicit use
of the cxx heap) is not a problem at the server side, this patch
nevertheless replaces the exception-based return-value handling to make
the code consistent with the ipc_call path.

Issue #3612
2022-02-15 10:10:02 +01:00
Norman Feske
3e4af3a567 base-hw: remove throw from ipc_call code path
This eliminates the dependency of the IPC-call operation from the cxx
heap.

Fixes #3612
2022-02-15 10:10:02 +01:00
Christian Helmuth
65284b29f8 depot: update recipe hashes 2022-01-19 12:38:13 +01:00
Norman Feske
3ba316b015 base-hw: declare build artifact for core 2022-01-19 12:38:12 +01:00
Stefan Kalkowski
426f52068b hw: avoid 'cps' instruction in ARM hyp mode
On some boards or emulators a CPU might be executing in hyp mode
when entering Genode's bootstrap code. In that mode the 'cps' instruction
is not defined. Therefore, we change the way the boot cpu is identified.

Ref #3415
2022-01-19 12:38:12 +01:00
Stefan Kalkowski
6bd7f167a4 hw: remove rpi1/3 board support
The code moved to https://github.com/skalk/genode-rpi

Ref #4363
2022-01-19 12:38:12 +01:00
Tomasz Gajewski
f79d5d640f hw: irq controller and timer improvements for Rpi
* renamed rpi pic to Bcm2835_pic
* renamed rpi3 pic to Bcm2837_pic
* added bcm2837 control for setting prescaler value (to fix timer_accuracy)
* changed handling of all interrupts for rpi3 by cascading to bcm2835 pic
* rpi3 irq controller base address made consistent with rpi
* added usb controller memory region for pic on rpi3 (for SOF interrupts)

Ref #3415
2022-01-19 12:38:12 +01:00
Norman Feske
5611fd2355 depot: update recipe hashes 2021-12-17 15:06:38 +01:00
Norman Feske
3cc6df3116 base: tighten affinity handling
This patch improves the robustness of the CPU-affinity handling.

- The types in base/affinity.h received the accessors
  'Location::within(space)' and 'Affinity::valid', which alleviates
  the fiddling with coordinates when sanity checking the values,
  in init or core.

- The 'Affinity::Location::valid' method got removed because its
  meaning was too vague. For sanity checks of affinity configurations,
  the new 'within' method is approriate. In cases where only the x,y
  values are used for selecting a physical CPU (during thread creation),
  the validity check (width*height > 0) was not meaningful anyway.

- The 'Affinity::Location::from_xml' requires a 'Affinity::Space'
  as argument because a location always relates to the bounds of
  a specific space. This function now implements the selection of
  whole rows or columns, which has previously a feature of the
  sandbox library only.

- Whenever the sandbox library (init) encounters an invalid affinity
  configuration, it prints a warning message as a diagnostic aid.

- A new 'Affinity::unrestricted' function constructs an affinity that
  covers the whole affinity space. The named functions clarifies
  the meaning over the previous use of the default constructor.

- Core's CPU service denies session requests with an invalid
  affinity parameter. Previously, it would fall back to an
  unrestricted affinity.

Issue #4300
2021-12-17 15:06:38 +01:00
Sebastian Sumpf
75509d77b5 base-hw: Remove 'riscv_qemu' and move to 'genode-riscv'
issue #4312
2021-12-17 15:04:48 +01:00
Norman Feske
890842dce2 base-hw/lib/mk/spec/cortex_a8/core-hw.inc (usb_armory) 2021-12-17 15:04:47 +01:00
Norman Feske
03047009b1 base: avoid implicit conversions
This patch is a prerequisite for compiling the code with
the warnings -Wconversion enabled.

Issue #23
2021-12-17 15:04:44 +01:00
Christian Helmuth
92b7be4d11 depot: update recipe hashes 2021-11-30 12:08:54 +01:00
Stefan Kalkowski
7eb3da71b5 base-hw: check managing_system property for SMC
* When issuing a secure-monitor-call on behalf of a PD session client
  first check the permission via the 'managing_system' property.

Fix #4321
2021-11-29 15:11:53 +01:00
Norman Feske
dc39a8db62 base: introduce Allocator::try_alloc
This patch changes the 'Allocator' interface to the use of 'Attempt'
return values instead of using exceptions for propagating errors.

To largely uphold compatibility with components using the original
exception-based interface - in particluar use cases where an 'Allocator'
is passed to the 'new' operator - the traditional 'alloc' is still
supported. But it existes merely as a wrapper around the new
'try_alloc'.

Issue #4324
2021-11-29 15:11:52 +01:00
Stefan Kalkowski
b12b0ed93d imx8q_evk: remove board support from repository
Moved to separate repo at https://github.com/skalk/genode-imx/

Fix #4301
2021-11-29 15:10:51 +01:00
Johannes Schlatow
7917c5d9ec Remove zynq_qemu platform and zynq nic driver
Moved to separate repo at https://github.com/jschlatow/genode-zynq

Fixes genodelabs/genode#4280
2021-11-29 15:10:51 +01:00
Christian Helmuth
abc9a2f232 depot: update recipe hashes 2021-10-14 13:46:25 +02:00
Johannes Schlatow
ef8a43c546 base-hw: cache maintenance
touch each page before flushing to ensure that it's present in the page table

genodelabs/genode#4279
2021-10-14 11:02:10 +02:00
Stefan Kalkowski
6789b86871 base-hw: optimize cache maintainance for ARMv8
* Remove the data-synchronization barrier from the inner-loop
* Instead add a system-wide barrier at the end of the operation

Fix #4269
2021-10-13 14:46:54 +02:00
Martin Stein
9542bcf88c base-hw: reduce includes in board.h
The includes for the address-space-ID allocator and the translation table are
usually specific to the CPU in use. Therefore these includes can be moved from
their current location in the board header to the CPU headers. This reduces the
number of decisions a board maintainer has to make if the CPU model he's aiming
for is already available.

This can probably also be applied for other includes in the board headers but I
intentionally leave it for a future commit as I don't have the time to do it
all now.

Ref #4217
2021-10-13 14:46:54 +02:00
Martin Stein
ad059362d2 base-hw: reduce hardware-specific include paths
For base-hw Core, we used to add quite some hardware-specific include paths
to 'INC_DIR'. Generic code used to include, for instance, '<cpu.h>' and
'<translation_table.h>' using these implicit path resolutions. This commit
removes hardware-specific include paths except for

1) the '<board.h>' include paths (e.g., 'src/core/board/pbxa9'),
2) most architecture-specific include paths (e.g., 'src/core/spec/arm_v7'),
3) include paths that reflect usage of virtualization or ARM Trustzone
   (e.g., 'src/core/spec/arm/virtualization').

The first category is kept because, in contrast to the former "spec"-mechanism,
the board variable used for this type of resolution is not deprecated and the
board headers are meant to be the front end of hardware-specific headers
towards generic code which is why they must be available generically via
'<board.h>'.

The second category is kept because it was suggested by other maintainers that
simple arch-dependent headers (like for the declaration of a CPU state) should
not imply the inclusion of the whole '<board.h>' and because the architecture
is given also without the former "spec"-mechanism through the type of the build
directory. I think this is questionable but am fine with it.

The third category is kept because the whole way of saying whether
virtualization resp. ARM Trustzone is used is done in an out-dated manner and
changing it now would blow up this commit a lot and exceed the time that I'm
willing to spend. This category should be subject to a future issue.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
49b09702b8 base-hw: don't include board.h from hardw. headers
The 'src/core/board/<board>/board.h' header is thought as front end of
hardware-specific headers of a given board towards the generic base-hw Core
code. Therefore it leads to problems (circular includes) if the board.h header
is included from within another hardware-specific header.

If hardware-specific headers access declarations from namespace Board in a
definition, the definition should be moved to a compilation unit that may
include board.h. If hardware-specific headers access declarations from board.h
in a declaration, they should either use the primary declaration from the
original header or, if the declaration must be selected according to the board,
another board-specific header should be introduced to reflect this abstraction.

This is applied by this commit for the current state of base-hw.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
5d74509b2d base-hw: get rid of static perf counter object
It is not necessary to have a class, an object, and a generic header for the
perfomance counter. The kernel merely enables the counter using cpu registers
('msr' instructions, no MMIO) on arm_v6 and arm_v7 only. Therefore this commit
makes the header arm-specific and replaces class and global static object with
a function for enabling the counter.

Fixes #4217
2021-10-13 14:46:53 +02:00
Martin Stein
b817e1977c base-hw: serial output as Main member
Let the kernel's serial-output driver be a member of the one Kernel::Main
object instead of having it as global static variable.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
910788313e base-hw: get rid of static variable in Kernel::Pd
Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
02f00a999c base-hw: global IRQ controller as Main member
Let the kernel's driver for the global IRQ controller be a member of the one
Kernel::Main object instead of having it as static variables in the drivers for
the local IRQ controllers. Note that this commit spares out renaming 'Pic' to
'Local_interrupt_controller' which would be more sensible now with the new
'Global_interrupt_controller' class. Furthermore, on ARM boards the commit
doesn't move 'Distributer' stuff to the new global IRQ controller class as they
don't have real data members (only MMIO) and can be instanciated for each CPU
anew. However, the right way would be to instanciate them only once in Main as
well.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
441d137482 base-hw: Address-Space-ID allocator as Main member
Let the kernel's Address-Space-ID allocator be a member of the one
Kernel::Main object instead of having it as global static variable.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
0c61b25bcf base-hw: no unmanaged_singleton in kernel thread
The unmanaged-singleton approach was used in this context only because of the
alignment requirement of the Core main-UTCB. This, however can also be achieved
with the new 'Aligned' utility, allowing the UTCB to be a member of the Core
main-thread object.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
b6641eaa25 base-hw: Core PD as Main member
Let the Core protection-domain object be a member of the one Kernel::Main
object instead of having it as global static variable.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
d6e347163d base-hw: unnecessary unmanaged-singleton includes
Remove some deprecated include directives for the unmanaged-singleton header.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
5dd8ee5840 base-hw: global IRQ pool as Main member
Let the global kernel IRQ-pool be a member of the one Kernel::Main object
instead of having it as global static variable.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
c49db16762 base-hw: don't use boot_info() outside main.cc
It's sufficient to access the boot info only on kernel initialization time.
Therfore, it can remain completely hidden to the rest of the kernel inside
kernel/main.cc in the initialization function.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
b247def09a base-hw: Core main-thread as Main member
Let the Core main-thread object be a member of the one Kernel::Main object
instead of having it as global static variable.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
2b89cd66cb base-hw: kernel CPU-pool as Main member
Let the kernel CPU-pool be a member of the one Kernel::Main object instead of
having it as global static variable.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
be3d5232c8 base-hw: kernel-data lock as Main member
Let the global kernel-data lock be a member of the one Kernel::Main object
instead of having it as global static variable.

Ref #4217
2021-10-13 14:46:53 +02:00
Martin Stein
82cf31ac27 base-hw: introduce Kernel::Main class
This commit introduces the Kernel::Main class that replaces the former way of
initializing the kernel (former 'kernel_init' function) and calling the C++
kernel entry handler (former 'kernel' function). These two are now
'Main::initialize_and_handle_kernel_entry' and 'Main::handle_kernel_entry'.
Also reading the execution time of the idle threads was already moved to
'Main'. The one static Main instance is meant to successivly replace all the
global static objects of the base-hw kernel with data members of the Main
instance making the data model of the kernel much more comprehensible. The
instance and most of its interface are hidden in kernel/main.cc. There are only
rare cases where parts of the Main interface must be accessible from the
outside. This should be done in the most specific way possible (see main.h)
and, if possible, without handing out references to Main data members or the
Main instance itself.

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
9de43a48b6 base-hw: conform pc board header
Normally, the board header can be found for each supported board under
'src/core/board/<BOARD>/board.h'. This was not the case for the board 'pc'
that was located under 'src/core/spec/x86_64/board.h'. The commit fixes this.

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
a9563bfd4c base-hw: rename Core_thread Core_main_thread
The class name Core_thread in Kernel for the object of the first thread of
core is too generic as there can be an arbitrary number of threads in core
besides this one. Furthermore, creating a core thread has its own syscall
'new_core_thread' that isn't related in any way to Core_thread. Therefore
this commit introduces the more specific name Core_main_thread as replacement
for Core_thread.

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
693a2b5421 base-hw: get rid of cpu_pool() in platform.cc
The function was only still used for reading the execution time of idle threads
of CPUs. Certainly, it is technically fine and more performant to read these
values directly from the kernel objects without doing a syscall. However,
calling cpu_pool() for it provides read and write access to a lot more than
only the execution time values. The interface via which Core directly reads
state of the kernel should be as narrow and specific as possible.
Perspectively, we want to get rid of the cpu_pool() accessor anyway. Therefore
this commit introduces Kernel::read_idle_thread_execution_time(cpu_idx) as
replacement. The function is implemented in kernel code and called by Core in
platform.cc.

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
277adcacb0 base-hw: make Trace_source in Platform() a class
Apparently, there is no need for exposing the data members of Trace_source, so,
we sould better make them private before someone gets the impression that they
are meant to be accessed directly.

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
aa6a7db50a base-hw: communicate kernel irqs via boot info
Core used to read the kernel-reserved IRQs from the timer objects in the
kernel's CPU objects and the PIC class (inter-processor IRQ). Besides not
being "good style" to access a kernel object in Core, this becomes a problem
when trying to prevent CPU pool from being accessed via global functions.

As a solution, this commit extends the boot info to also carry an array of all
kernel-reserved IRQs.

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
8b69bc96f9 base-hw: separate variants of Kernel_object(...)
For the constructor of Kernel_object<T> there are two variants. One for the
case that it is called from Core where the kernel object (type T) must be
created via a syscall and one when it is called from within the kernel and the
kernel object can be created directly. Selecting one of these variants was done
using a bool argument to the constructor. However, this implies that the
constructor of Kernel_object<T> and that of T have the same signature in the
variadic arguments, even in the syscall case, although technically it would
then not be necessary.

This becomes a problem as soon as kernel objects created by Core shall receive
additional arguments from the kernel, for instance a reference to the global
CPU pool, and therefore stands in the way when wanting to get rid of global
statics in the kernel. Therefore, this commit introduces two constructors that
are selected through enum arguments:

! Kernel_object(Called_from_kernel, ...);
! Kernel_object(Called_from_core, ...);

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
6e4ef43bf0 base-hw: always use 'unsigned' for priorities
At some points in the code, 'signed' was used instead of the more appropriate
'unsigned' type.

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
b922dc5c10 base-hw: fix self-include in kernel/types.h
That this header apparently used to include itself didn't cause any problems
so far but still remained bad style.

Ref #4217
2021-10-13 14:46:52 +02:00
Christian Helmuth
83c5648d33 depot: update recipe hashes 2021-08-30 15:00:39 +02:00
Christian Helmuth
7618c9410a depot: update recipe hashes 2021-08-18 15:06:12 +02:00
Christian Helmuth
fce525f122 depot: update recipe hashes 2021-07-28 11:27:05 +02:00
Stefan Kalkowski
f939b9ffb5 base-hw: print addr as hex value in cache warning
Ref #4207
2021-07-28 11:25:21 +02:00
Sebastian Sumpf
4b10aa94ec base-hw: save/restore fpcr register for ARM_V8
The floating-point (fpcr) control register is user land accessible and
controls, for example, rounding mode.

fixes #3723 and related to #4213
2021-07-28 11:25:20 +02:00
Christian Helmuth
ece33d37f8 depot: update recipe hashes 2021-06-25 11:46:37 +02:00
Stefan Kalkowski
e7067050be base: extend cache maintainance functionality
Introduce two new cache maintainance functions:
* cache_clean_invalidate_data
* cache_invalidate_data
used to flush or invalidate data-cache lines.

Both functions are typically empty, accept for the ARM architecture.
The commit provides implementations for the base-hw kernel, and Fiasco.OC.

Fixes #4207
2021-06-25 11:43:41 +02:00
Christian Helmuth
1d52bd017d depot: update recipe hashes 2021-05-28 14:16:46 +02:00
Stefan Kalkowski
9f099bd61c base-hw: use generalized util/array.h
Issue #4170
2021-05-28 14:16:45 +02:00
Alexander Boettcher
509e5aa776 platform(x86): report features via platform_info
Report via platform_info the capabilities of the kernel, e.g. ACPI and MSI.

With the commit the try-catch pattern on IRQ session creation by the platform
driver is avoided.

Issue #4016
2021-05-28 14:16:44 +02:00
Christian Helmuth
777923f9bd depot: update recipe hashes 2021-05-10 11:18:12 +02:00
Norman Feske
516a9a6925 depot: update recipe hashes 2021-05-05 11:35:31 +02:00
Christian Prochaska
c4e3d3dbc4 hw: fix build error with gcc 10
Fixes #4115
2021-05-05 11:35:30 +02:00
Norman Feske
efbed6f7bf depot: update recipe hashes 2021-04-20 12:10:58 +02:00
Norman Feske
dc89ebf978 core: kernel-agnostic 'Mapping' type
This patch unifies the core-internal 'Mapping' type across all base
platforms.

As one minor downside on seL4, the diagnostic error messages when
observing faults other than page faults no longer print the faulting
thread and PD names.

Issue #2243
2021-04-20 12:10:57 +02:00
Norman Feske
468e7a825c base/cache.h: rename Cache_attribute to Cache
The short name is better because the type will become prominently
visible at the API.

Issue #2243
2021-04-20 12:10:31 +02:00
Norman Feske
0f9cb72cfa depot: update recipe hashes 2021-03-29 13:46:49 +02:00
Jean-Adrien DOMAGE
32169cd137 add I2c driver for imx8q based platform
This commit introduces a new i2c driver for the imx8q_evk based platform.

Fixes #4052
2021-03-29 13:45:24 +02:00
Norman Feske
5c5b56d1e0 depot: update recipe hashes 2021-03-12 12:08:24 +01:00
Sebastian Sumpf
6223ae4413 riscv: Interrupt controller support
- Enable the "platform-level interrupt controller" PLIC on base-hw
- The RISC-V specification offers only a register description, but no
  layout for the register set. This implies the layout is platform
  dependent, and therefore, implemented separately for Qemu

issue #4042
2021-03-12 12:01:38 +01:00
Norman Feske
aa0a98bd43 base-foc/hw: avoid use of placement new operator
Fixes #2106
2021-03-12 12:01:38 +01:00
Norman Feske
c68443e2eb base-hw: support packaging of multi-arch boards
With this patch, the board/<name>/arch property file can have multiple
lines where each line denotes an instruction-set architecture supported
for the board.

Issue #4019
Fixes #4034
2021-03-12 12:01:36 +01:00
Sebastian Sumpf
d4b58b689c base-hw: fix RISC-V duration calculation
Simplify calculation of Timer::_duration, the old implementation caused
the time running backwards sometimes. This makes
'nic_router_dhcp_*' and 'event_filter' run scripts succeed.

issue #4021
2021-03-12 12:01:36 +01:00
Christian Helmuth
0afd3db894 depot: update recipe hashes 2021-02-25 11:24:23 +01:00
Sebastian Sumpf
f68e655312 mk: link core to library archive instead of .o file
Do not link base and core libraries into on large relocatable .o file,
which is linked later to core - causing long link times. Create an
independent library archive out of the base and core libraries that can
be linked faster.

issue #4027
2021-02-23 12:17:04 +01:00
Norman Feske
64165d829e depot: update recipe hashes 2021-02-23 12:07:18 +01:00
Christian Helmuth
219809ffed base: refactor VM/vCPU API
Issue #3554
2021-02-23 12:07:18 +01:00
Sebastian Sumpf
ca777fe93f riscv: add riscv_qemu base-hw recipe
issue #4021
2021-02-23 12:07:16 +01:00
Sebastian Sumpf
ccd9ba4161 riscv: move CPU header from base-hw to base
issue #4021
2021-02-23 12:07:16 +01:00
Sebastian Sumpf
f5cd12dcf9 base/base-hw: unify startup library builds
- Use 'select_from_repositories' for crt0.s of startup library
- Move RISC-V crt0.s to base (where the other archs are located)

issue #4019
2021-02-23 12:07:15 +01:00
Norman Feske
db3f86d603 base-hw: avoid double slashes in path names 2021-02-23 12:02:45 +01:00
Norman Feske
fa68325a57 base-hw: streamline extraction of depot archives
This patch simplifies the packaging of the base-hw kernel for a given
board, in particular when the board support is hosted as an external
repository such as genode-world. Regardless of where the board-support
is hosted, the content.mk file becomes as simple as:

  include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc

The board name is automatically inferred from the path of the src
recipe. The architecture is determined from board/<name>/arch files,
following the pattern of the image_link_address. The attempt to build a
base-hw-<board> binary archive for the wrong architecture is now
gracefully handled by skipping all targets (using the REQUIRES
mechanism).

Besides the improved convenience, the patch results in depot archives
that are much closer tailored to the actual board by omitting files for
architectures that are not used by the board. E.g., the src/base-hw-pc
archive does not contain any ARM-related content.

The patch also restores the package builds for core/bootstrap object
files as a follow-up fix of "base: remove SPEC variables of boards",
which happened to left 'BOARD' undefined in the src archives.

Fixes #4019
2021-02-23 12:02:45 +01:00
Sebastian Sumpf
fd0e6685fc riscv: Use Qemu and update to ISA v1.10
- remove Spike/BBL support in favour of Qemu (>=4.2.1)
- add 'riscv_qemu' board, remove 'spike' board'
- update to privileged ISA v1.10 (from v1.9.1)
- use direct system calls for privileged core threads (they call into
  the kernel and don't use mode changing system calls, i.e. 'ecall',
  semantics)
- use 'OpenSBI' semtantics for SBI calls (to machine mode) instead of
  BBL

issue #4012
2021-02-23 12:02:44 +01:00
Norman Feske
493924a35e base-hw: coding style
Improve consistency with the other base repositories, in particular

- Indentation of class initializers
- Vertical whitespace around control-flow statements
- Preferably place control-flow statements (return, break, continue) at
  beginning of a line
- Placing the opening brace of a namespace at the end of line
- Placing the opening brace of a class at a new line
- Removing superfluous braces around single statements
- Two empty lines between methods/functions in implementation files
2021-02-23 12:02:41 +01:00
Norman Feske
8cc2662aac Remove support for the Muen separation kernel
Fixes #3995
Fixes #3994
2021-02-23 11:55:44 +01:00
Norman Feske
a981fb864c depot: update recipe hashes 2021-01-25 14:00:43 +01:00
Norman Feske
c4cf9b6e6d base-hw: introduce board-property directories
This patch moves the bootstrap-link-address information from the
tool/run/boot_dir/hw file to board-specific property files that can be
accessed by using the board as key. This eliminates the need to
customize boot_dir/hw when hosting board-support in an external
repository.

Fixes #3998
2021-01-25 14:00:43 +01:00
Piotr Tworek
8f6b934caa base-hw: Fully define _crt0_start_stack value on arm_64
The _crt0_start_stack label points to a memory location containing the
size of the bootstrap stack. On AArch64 this should be an 8 byte value,
but the code only only defines half of those using asm .long statement.
The other half is expected to be 0, which is true when using GNU as.
This is not the case when using clang's integrated as however. Since
_crt0_stack_size is defined inside .text section clang uses 0xd503201f
value (aarch64 nop instruction) to fill the extra 4 bytes.

Fix this minor incompatibility by explicitly defining both halfs of
this 8 byte quantity.

Fixes #3987
2021-01-25 14:00:43 +01:00
Norman Feske
1ccf8a280c base-hw: simplify board support in external repo
Avoid use of REP_DIR in *.mk files to simplify the use of these files as
templates for a board hosted in a separate repository.

Use REP_INC_DIR for searching headers, thereby considering headers
hosted in an external repository.

Issue #3168
2021-01-25 13:58:10 +01:00
Stefan Kalkowski
bdd923406f base: remove SPEC variables of boards (fix #3971)
* Remove SPEC declarations from mk/spec
* Remove all board-specific REQUIRE declaratiions left
* Replace [have_spec <board>] run-script declarations with have_board where necessary
* Remove addition of BOARD variable to SPECS in toplevel Makefile
* Move board-specific directories in base-hw out of specs
2021-01-25 13:58:09 +01:00
Pirmin Duss
a4d5687510 base-hw: allow out of tree imx8 platforms
Issue #3911
2021-01-25 13:58:09 +01:00
Alexander Boettcher
2b0170fb6a base-hw: ack thread capability on construction
Fixes #3982
2021-01-25 13:58:09 +01:00
Norman Feske
f57519397b Remove Pd_session::Native_pd definition from API
This type can be a forward declaration in the public API because its
definition is required only in kernel-specific code.

Fixes #3979
2021-01-25 12:51:54 +01:00
Tomasz Gajewski
98798f18b5 Fix minor inconsistencies in mk files
Fixes #3972
2021-01-25 12:50:54 +01:00
Christian Helmuth
1bef11accf depot: update recipe hashes 2020-12-18 09:10:52 +01:00
Christian Helmuth
f2e0c164c2 depot: update recipe hashes 2020-11-27 09:21:06 +01:00
Alexander Boettcher
774b1f4277 base: remove Thread_deprecated
Fixes #3954
2020-11-27 09:19:08 +01:00
Piotr Tworek
5db2971903 base-hw/arm_v7a: Mark r1 as out in Kernel::call64
In case of arm_v7a Kernel::call64 the syscall will use both r0 and r1 as
output registers. Unfortunately the inline asm does not reflect this and
only r0 is explicitly specified as output. GCC manages to produce output
which we'd like to see. Clang on the other hand takes adventage of the fact
r1 should not be touched by swi and produces fewer instructions which do
what the code describes, but not what we actually want.

Basically the code which we want and is generated by GCC is:
  svc     0
  mov     r2, r0
  mov     r0, r1
  mov     r1, r2
  bx      lr

Clang on the other hand generates correct assembly given the code, but
incorrect given what the function is supposed to do:
  svc     0
  mov     r1, r0
  mov     r0, #0
  bx      lr

Both GCC and clang generate the same, expected assembly output when r1
is marked as output register from the inline asm swi call.

Fixes #3951
2020-11-27 09:19:08 +01:00
Piotr Tworek
50ab86cd72 base-hw: Remove unused rdtsc function for x86_64
This function has no callers. Clang warns about this.

Issue #3950
2020-11-27 09:19:08 +01:00
Piotr Tworek
a892018926 base-hw: Define Entry function as noreturn.
Right now the code marks specific instance of this function as noreturn.
It then tries to initialize it using a value that has the same type,
except for the noreturn part. GCC does not care, but clang complains this
technically assigns the value of entry from incompatible pointer type.

Fix this by defining Entry function as no return.

Issue #3938
2020-11-23 12:02:59 +01:00
Piotr Tworek
1643d623e4 base-hw: Fix warning about unused lambda capture
The lambda function passed to Board::Vm_page_table_array does not
actually use "this" for anything. GCC does not warn about this, but
clang does. Remove the extra capture to make clang happy.

Issue #3938
2020-11-23 12:02:59 +01:00
Piotr Tworek
9b84a8a402 base-hw: Add semicolons after [[fallthrough]]
GCC doesn't care, but clang complains if [[fallthrough]] is not followed
by a semicolon. Existing code is also not consitent in this regard. Lets
just fix it to make clang happy.

Issue #3938
2020-11-23 12:02:59 +01:00
Stefan Kalkowski
7298b00013 base-hw: make ARMv7/v8 hypervisor smp ready
* Introduce hypervisor-stack per CPU
* Introduce host world context per CPU
* Mark EL2 translation table memory as inner shareable
* The VMID is not bound to a single VCPU, but to the Vm_session as a whole
* Set affinity of the VCPU accordingly
* Add VMPIDR to VM state

Ref #3926
2020-11-23 12:02:58 +01:00
Stefan Kalkowski
1d826a2c48 base-hw: do direct syscall when run/pause a VCPU
Instead of calling core to run/pause a VCPU, go directly to the kernel.
Apart from the performance win, it would otherwise involve a more complex
protocol, when a VCPU on another core has to be removed from the scheduler.
Core's entrypoint handling those request runs on the boot-cpu only.

Ref #3926
2020-11-23 12:02:58 +01:00
Stefan Kalkowski
40445d7011 base: extend vm_session API with native vcpu cap
To enable the interaction of a VMM with the kernel directly,
a hidden RPC gets introduced. It allows a kernel-specific
base-library implementation of the Vm_session::Client to request
a kernel-specific capability to address a VCPU, e.g., to
run/stop it.

Ref #3926
2020-11-23 12:02:58 +01:00
Christian Prochaska
798beab30e base: support process-local signal submission
Issue #3923
2020-11-23 12:02:53 +01:00
Christian Prochaska
50e0f3b977 base: don't throw exceptions in 'Signal_receiver::pending_signal()'
Issue #3922
2020-11-23 12:02:49 +01:00
Christian Helmuth
5be1c793a5 depot: update recipe hashes 2020-10-23 14:16:38 +02:00
Christian Helmuth
91f8281618 depot: update recipe hashes 2020-10-09 13:35:57 +02:00
Sebastian Sumpf
27f705bc48 bootstrap: iomux adaptions for i.MX8 MIPI
These settings were obtained with a JTAG debugger from a running Linux
system. They work for MIPI as well as for HDMI.

issue #3900
2020-10-09 13:35:56 +02:00
Martin Stein
7feea78991 timeout: rework timeout framework
* get rid of alarm abstraction
* get rid of Timeout::Time type
* get rid of pointer arguments
* get rid of _discard_timeout indirection
* get rid of 65th bit in stored time values
* get rid of Timeout_scheduler interface
* get rid of uninitialized deadlines
* get rid of default arguments
* get rid of Timeout::_periodic
* get rid of Timeout::Raw
* use list abstraction
* only one interface for timeout handlers
* rework locking scheme to be smp safe
* move all method definitions to CC file
* name mutexes more accurate
* fix when & how to set time-source timeout
* fix deadlocks

Fixes #3884
2020-10-09 13:35:56 +02:00
Stefan Kalkowski
bbb017dc24 muen: update to Community 2019 toolchain version
Fix #3903
2020-10-09 13:35:55 +02:00
Alexander Boettcher
90bea1499e core: store new affinity on successful migration
Adjust the base-* platforms to acknowledge new thread location solely if
migration is supported and succeeded. Otherwise the wrong thread
locations are observed via the trace session and utilization time calculation
get wrong.

Issue #3842
2020-10-09 13:33:36 +02:00
Martin Stein
1b41d9db90 base: remove alarm library from base
Ref #3884
2020-10-09 13:33:36 +02:00
Christian Helmuth
c59c266afc depot: update recipe hashes 2020-09-17 14:23:14 +02:00
Stefan Kalkowski
d7eb174c88 muen: fix building on modern devel distros
* Use python2 interpreter not available by default explicitely
* Update ada-bfd binding library to meet binutils-dev >= 2.34
2020-09-17 10:14:07 +02:00
Christian Helmuth
c649307720 depot: update recipe hashes 2020-08-28 08:29:12 +02:00
Norman Feske
7d0cb9620b depot: update recipe hashes 2020-08-25 11:50:41 +02:00
Stefan Kalkowski
5f5ad41ad3 hw: unify irq enumeration for Raspberri Pi
By now, the enumeration of peripheral interrupts on Raspberry Pi 1 was
different in between base-hw kernel and Fiasco.OC. Therefore, hacks were
needed in every driver to request the correct interrupt number dependent
on the kernel. Before reproducing the same in the platform driver for rpi,
we can more easily use the same enumeration with base-hw.

Ref #3864
2020-08-25 11:50:12 +02:00
Stefan Kalkowski
70f98fcc44 hw: implement Pd_session::managing_system for ATF
To access the ARM Trusted Firmware from the platform driver
fill the new `managing_system` call of the PD session with life resp.
do a SMC call on behalf of the client.

Fix #3816
2020-08-25 11:50:11 +02:00
Christian Prochaska
fd682cd470 hw: check descriptor validity in LPAE lookup
Fixes #3828
2020-07-30 08:49:23 +02:00
Alexander Boettcher
41380ff769 base: remove Cancelable_lock
- base/cancelable_lock.h becomes base/lock.h
- all members become private within base/lock.h
- solely Mutex and Blockade are friends to use base/lock.h

Fixes #3819
2020-07-30 08:49:23 +02:00
Norman Feske
de795b1a6e depot: update recipe hashes 2020-07-13 11:33:53 +02:00
Alexander Boettcher
f3efbe50bb base: remove deprecated cancel_blocking() support
for threads.

Fixes #3806
2020-07-13 11:33:12 +02:00
Norman Feske
4450b37ff5 depot: update recipe hashes 2020-06-29 14:25:28 +02:00
Stefan Kalkowski
1f91fd3f7d hw: scale imx8q_evk cpu to 1.5 GHz 2020-06-29 14:25:27 +02:00
Norman Feske
eb3a81a874 depot: update recipe hashes 2020-06-22 09:39:41 +02:00
Stefan Kalkowski
04d8c859d8 hw: enable branch predictor on rpi
* Z-bit was never enabled for rpi1
* Write buffer, and TCM bits are deprecated in this processor generation
  so do not use them

Ref #3247
2020-06-22 09:39:40 +02:00
Christian Helmuth
6006051fb9 depot: update recipe hashes 2020-05-27 11:56:47 +02:00
Norman Feske
0f27d139bd depot: update recipe hashes 2020-05-18 10:16:59 +02:00
Norman Feske
dd899fde29 depot: update recipe hashes 2020-04-24 14:37:57 +02:00
Norman Feske
b134867f31 Remove Rpc_entrypoint::Native_context
This patch largely reverts the commit "base: lay groundwork for
base-linux caps change" because the use of 'epoll' instead of 'select'
alleviated the need to allocate large FD sets, which motivated the
introduction of the 'Native_context' hook.

Related to issue #3581
2020-04-21 16:50:37 +02:00
Stefan Kalkowski
9f28f4f803 hw: avoid BASE_DIR relative path definitions
Fix #3728
2020-04-17 12:55:13 +02:00
Stefan Kalkowski
0e49336b96 Retire Exynos 5 support (fix #3725) 2020-04-17 12:53:57 +02:00
Stefan Kalkowski
941e918b46 vmm: unify armv7/v8 virtualization
Fix #3638
2020-04-17 12:52:02 +02:00
Stefan Kalkowski
74e75d7fbc hw: enable virtualization support for virt_qemu
Ref #3638
2020-04-17 12:51:53 +02:00
Stefan Kalkowski
58db6542f8 hw: check for security extension support in GICv2
Ref #3638
2020-04-17 12:51:44 +02:00
Christian Helmuth
b60b591d06 depot: update recipe hashes 2020-04-17 12:40:13 +02:00
Stefan Kalkowski
ff378a8c5b hw: cache maintainance on mapping removal too
Older ARM processors like ARMv6, or Cortex A8 need to write back changes
of the page-tables to physical ram because the MMU does not use the cache.
This naturally needs to be done not only when adding a mapping,
but on removal too.

Fix #3715
2020-04-17 12:40:13 +02:00
Alexander Boettcher
3956530634 base: use Mutex/Blockade
Issue #3612
2020-04-17 12:40:12 +02:00
Alexander Boettcher
e87d60ddf7 core: use Mutex/Blockade
Issue #3612
2020-04-17 12:40:12 +02:00
Stefan Kalkowski
f051065582 Retire OMAP4 support
Fix #2850
2020-04-17 12:39:32 +02:00
Piotr Tworek
585c4b8c69 hw: Add support for Qemu virt arm platforms.
This patch adds support for booting base-hw kernel on qemu-arm virt
machines. The arm_virt machine has 2GB of RAM, 2 Cortex A15 cores and
uses GICv2 interrupt controller. The arm_64_virt machine also has 2GB of
RAM, but has 4 Cortex A53 cores and uses GICv3. Both machines use PSCI
to boot additional CPU cores.

Fixes #3673
2020-04-17 12:39:32 +02:00
Piotr Tworek
dad1de1865 hw: Add interface for making basic ARM PSCI calls.
So far this only exposes two functions allowing the code to turn on
additional CPUs. There is much more functionality defined by PSCI spec
but so far its not needed by Genode.

Fixes #3672
2020-04-17 12:39:32 +02:00
Norman Feske
46fa8197a2 depot: update recipe hashes 2020-03-26 11:39:02 +01:00
Stefan Kalkowski
256b2fa3e1 hw: cortex a9 diagnostic register fixup
This is a follow-up fix for commit 202333c881.
It checks for the diagnostic registers being already setup correctly.
Otherwise on platforms with secure firmware, like Pandaboard it will stuck.

Ref #3639
2020-03-26 11:39:02 +01:00
Norman Feske
0f3ac4cb9f base-hw: let upgrade_cap_slab reflect Out_of_caps
This patch reflects the Out_of_caps exception from core to the client,
in addition to the already covered Out_of_ram exception. It thereby
eliminates a potential abort in core, which I observed with the
tool_chain_auto.run script:

  Kernel: RPC upgrade_cap_slab
  Error: Uncaught exception of type 'Genode::Quota_guard<Genode::Cap_quota>::Limit_exceeded'
  Warning: abort called - thread: entrypoint

In addition to propagating the exception, the patch add the client-side
exception-handling code to the base library.

Fixes #3703
2020-03-26 11:38:59 +01:00
Stefan Kalkowski
6d48b5484d hw: correct the ARM cache maintainance operations
This commit fixes the following issues regarding cache maintainance
under ARM:

* read out I-, and D-cache line size at runtime and use the correct one
* remove 'update_data_region' call from unprivileged syscalls
* rename 'update_instr_region' syscall to 'cache_coherent_region' to
  reflect what it doing, namely make I-, and D-cache coherent
* restrict 'cache_coherent_region' syscall to one page at a time
* lookup the region given in a 'cache_coherent_region' syscall in the
  page-table of the PD to prevent machine exceptions in the kernel
* only clean D-cache lines, do not invalidate them when pages where
  added on Cortex-A8 and ARMv6 (MMU sees phys. memory here)
* remove unused code relicts of cache maintainance

In addition it introduces per architecture memory clearance functions
used by core, when preparing new dataspaces. Thereby, it optimizes:

* on ARMv7 using per-word assignments
* on ARMv8 using cacheline zeroing
* on x86_64 using 'rept stosq' assembler instruction

Fix #3685
2020-03-26 11:38:55 +01:00
Alexander Boettcher
e096202b1f hw/x86: use PAT for write combining support
Fixes #3623
2020-03-26 11:38:54 +01:00
Alexander Boettcher
44ace04b95 hw/x86: add cpuid register macro
Issue #3623
2020-03-26 11:38:54 +01:00
Alexander Boettcher
507a34b3d0 hw/x86: implement wrmsr in macro
Issue #3623
2020-03-26 11:38:54 +01:00
Christian Helmuth
5affd51250 depot: update recipe hashes 2020-02-28 08:59:43 +01:00
Stefan Thöni
a7a9855493 base: lay groundwork for base-linux caps change
Include the necessary hooks to introduce file descriptor
based capabilities in base linux.

Issue #3581
2020-02-27 14:46:58 +01:00
Christian Helmuth
4cccf74664 depot: update recipe hashes 2020-02-20 12:11:23 +01:00
Stefan Kalkowski
8cc48d5688 hw: be more accurate in synchronizing ASID/Pages
Fix #3651
2020-02-20 12:11:23 +01:00
Alexander Boettcher
5440cd4b50 base: use blockade in thread
Issue #3612
2020-02-20 12:11:22 +01:00
Alexander Boettcher
00f69bc70d base: add mutex as derivate of lock
The mutex class is more restrictive in usage compared to
Genode::Lock.

- At initialiation time it is ever unlocked.
- No thread is permitted to lock twice. Warn about it
  in case it happens.
- Only the lock onwer is permitted to unlock the mutex.
  Warn about it and don't unlock the mutex in case it happens.

Issue #3612
2020-02-20 12:11:22 +01:00
Stefan Kalkowski
725d16e18e hw: optimize ipc capability allocation
In preparation of ipc receive, by now a bunch of capabilities got
allocated to be ready iin case of capability receiption. After that
unuse slots were freed again. This overhead of senseless (de-)allocations
is replaced in this commit by just restock capability slots that got
used by the last receive.

Fix #3640
2020-02-20 12:11:22 +01:00
Martin Stein
e42a205a51 base-hw: Ada-compliant scheduler method signatures
Ref #3308
2020-02-20 12:11:22 +01:00