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base-hw: Enable caches on ARM v6

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This commit is contained in:
Norman Feske 2013-04-08 19:04:45 +02:00
parent d43d9900ab
commit 65f20262cb
3 changed files with 6 additions and 28 deletions
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8
base-hw/src/core/tlb/arm.h
View File

@ -132,14 +132,6 @@ namespace Arm
ap_bits[Page_flags::W::get(flags)][Page_flags::K::get(flags)];
}
/**
* Wether support for caching is already enabled
*
* FIXME: Normally all ARM platforms should support caching,
* but for some 'base_hw' misses support by now.
*/
inline bool cache_support();
/**
* Memory region attributes for the translation descriptor 'T'
*/

12
base-hw/src/core/tlb/arm_v6.h
View File

@ -89,9 +89,6 @@ namespace Arm_v6
}
bool Arm::cache_support() { return 0; }
template <typename T>
static typename T::access_t
Arm::memory_region_attr(Arm::Page_flags::access_t const flags)
@ -106,13 +103,10 @@ Arm::memory_region_attr(Arm::Page_flags::access_t const flags)
if(Arm::Page_flags::D::get(flags))
return 0;
if(cache_support()) {
if(Arm::Page_flags::C::get(flags))
return Tex::bits(5) | C::bits(0) | B::bits(1);
if(Arm::Page_flags::C::get(flags))
return Tex::bits(5) | C::bits(0) | B::bits(1);
return Tex::bits(6) | C::bits(1) | B::bits(0);
}
return Tex::bits(4) | C::bits(0) | B::bits(0);
return Tex::bits(6) | C::bits(1) | B::bits(0);
}
#endif /* _TLB__ARM_V6_H_ */

14
base-hw/src/core/tlb/arm_v7.h
View File

@ -126,19 +126,11 @@ Arm::memory_region_attr(Arm::Page_flags::access_t const flags)
if(Arm::Page_flags::D::get(flags))
return Tex::bits(2) | C::bits(0) | B::bits(0);
if(cache_support()) {
if(Arm::Page_flags::C::get(flags))
return Tex::bits(5) | C::bits(0) | B::bits(1);
if(Arm::Page_flags::C::get(flags))
return Tex::bits(5) | C::bits(0) | B::bits(1);
return Tex::bits(6) | C::bits(1) | B::bits(0);
}
return Tex::bits(4) | C::bits(0) | B::bits(0);
return Tex::bits(6) | C::bits(1) | B::bits(0);
}
bool Arm::cache_support() { return 1; }
#endif /* _TLB__ARM_V7_H_ */