From 65f20262cbd253a7b6e19abfcc45d68a26468860 Mon Sep 17 00:00:00 2001 From: Norman Feske Date: Mon, 8 Apr 2013 19:04:45 +0200 Subject: [PATCH] base-hw: Enable caches on ARM v6 --- base-hw/src/core/tlb/arm.h | 8 -------- base-hw/src/core/tlb/arm_v6.h | 12 +++--------- base-hw/src/core/tlb/arm_v7.h | 14 +++----------- 3 files changed, 6 insertions(+), 28 deletions(-) diff --git a/base-hw/src/core/tlb/arm.h b/base-hw/src/core/tlb/arm.h index 69d264c613..5df9064896 100644 --- a/base-hw/src/core/tlb/arm.h +++ b/base-hw/src/core/tlb/arm.h @@ -132,14 +132,6 @@ namespace Arm ap_bits[Page_flags::W::get(flags)][Page_flags::K::get(flags)]; } - /** - * Wether support for caching is already enabled - * - * FIXME: Normally all ARM platforms should support caching, - * but for some 'base_hw' misses support by now. - */ - inline bool cache_support(); - /** * Memory region attributes for the translation descriptor 'T' */ diff --git a/base-hw/src/core/tlb/arm_v6.h b/base-hw/src/core/tlb/arm_v6.h index 39828043c8..51328496b0 100644 --- a/base-hw/src/core/tlb/arm_v6.h +++ b/base-hw/src/core/tlb/arm_v6.h @@ -89,9 +89,6 @@ namespace Arm_v6 } -bool Arm::cache_support() { return 0; } - - template static typename T::access_t Arm::memory_region_attr(Arm::Page_flags::access_t const flags) @@ -106,13 +103,10 @@ Arm::memory_region_attr(Arm::Page_flags::access_t const flags) if(Arm::Page_flags::D::get(flags)) return 0; - if(cache_support()) { - if(Arm::Page_flags::C::get(flags)) - return Tex::bits(5) | C::bits(0) | B::bits(1); + if(Arm::Page_flags::C::get(flags)) + return Tex::bits(5) | C::bits(0) | B::bits(1); - return Tex::bits(6) | C::bits(1) | B::bits(0); - } - return Tex::bits(4) | C::bits(0) | B::bits(0); + return Tex::bits(6) | C::bits(1) | B::bits(0); } #endif /* _TLB__ARM_V6_H_ */ diff --git a/base-hw/src/core/tlb/arm_v7.h b/base-hw/src/core/tlb/arm_v7.h index 92efa809cc..59760b3cd9 100644 --- a/base-hw/src/core/tlb/arm_v7.h +++ b/base-hw/src/core/tlb/arm_v7.h @@ -126,19 +126,11 @@ Arm::memory_region_attr(Arm::Page_flags::access_t const flags) if(Arm::Page_flags::D::get(flags)) return Tex::bits(2) | C::bits(0) | B::bits(0); - if(cache_support()) { - if(Arm::Page_flags::C::get(flags)) - return Tex::bits(5) | C::bits(0) | B::bits(1); + if(Arm::Page_flags::C::get(flags)) + return Tex::bits(5) | C::bits(0) | B::bits(1); - return Tex::bits(6) | C::bits(1) | B::bits(0); - } - return Tex::bits(4) | C::bits(0) | B::bits(0); + return Tex::bits(6) | C::bits(1) | B::bits(0); } - - -bool Arm::cache_support() { return 1; } - - #endif /* _TLB__ARM_V7_H_ */