openwrt/target/linux/ramips/dts/mt7628an_tplink_archer-c20-v4.dts
Adrian Schmutzler e6a181dcea ramips: simplify status for ehci/ohci on mt7628 TP-Link devices
At the moment, ehci/ohci is enabled in mt7628an SoC DTSI, then
disabled in the TP-Link-specific DTSI files, and finally enabled
again in the DTS files of the devices needing it.

This on-off-on scheme is hard to grasp on a quick look. Thus, this
patch drops the status in the TP-Link-specific DTSI files, having
the TP-Link devices treated like the rest of mt7628an DTSes, i.e.
ehci/ohci is enabled by default and needs to be disabled explicitly
where needed.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2020-12-07 14:22:00 +01:00

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#include "mt7628an_tplink_8m.dtsi"
/ {
compatible = "tplink,archer-c20-v4", "mediatek,mt7628an-soc";
model = "TP-Link Archer C20 v4";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
leds {
compatible = "gpio-leds";
lan {
label = "green:lan";
gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
};
led_power: power {
label = "green:power";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
};
wan {
label = "green:wan";
gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
};
wan_orange {
label = "orange:wan";
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
};
wlan5g {
label = "green:wlan5g";
gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
wlan2g {
label = "green:wlan2g";
gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
wps {
label = "green:wps";
gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
rfkill {
label = "rfkill";
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
};
};
&ehci {
status = "disabled";
};
&ohci {
status = "disabled";
};
&wmac {
mtd-mac-address-increment = <(-2)>;
};
&esw {
mediatek,portmap = <0x3e>;
};
&state_default {
gpio {
groups = "i2s", "gpio", "refclk", "p0led_an", "p1led_an", "p2led_an", "p3led_an", "p4led_an", "wdt";
function = "gpio";
};
};
&pcie {
status = "okay";
};
&pcie0 {
mt76@0,0 {
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x28000>;
ieee80211-freq-limit = <5000000 6000000>;
mtd-mac-address = <&factory 0xf100>;
mtd-mac-address-increment = <(-1)>;
};
};