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aafee2b3e9
The first gpio controller (gpio or gpio0) is always enabled by default in the SoC DTSI files. No need to set status=okay in the device DTS files a second time. Remove the redundant statements. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
147 lines
2.1 KiB
Plaintext
147 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "bdcom,wap2100-sk", "ralink,mt7620a-soc";
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model = "BDCOM WAP2100-SK";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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leds {
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compatible = "gpio-leds";
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usb {
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label = "green:usb";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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trigger-sources = <&ohci_port1>, <&ehci_port1>;
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linux,default-trigger = "usbport";
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};
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led_power: wps {
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label = "green:wps";
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gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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};
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wlan2g {
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label = "green:wlan2g";
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gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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};
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};
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keys {
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compatible = "gpio-keys";
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wps {
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label = "wps";
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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reset {
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label = "reset";
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gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x50000 0xf70000>;
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};
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};
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gpio3 {
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status = "okay";
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};
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&sdhci {
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status = "okay";
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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ðernet {
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mtd-mac-address = <&factory 0x4>;
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mediatek,portmap = "wllll";
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};
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&wmac {
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ralink,mtd-eeprom = <&factory 0x0>;
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&state_default {
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default {
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groups = "spi refclk", "uartf", "wled";
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function = "gpio";
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};
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};
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